CINECA IRIS Institutional Research Information System
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishIn this paper, simple circuital techniques to design efficient pulse triggered flip-flops are presented.The proposed approach aims at considerably alleviating the detrimental effects of current contentionmechanisms, occurring at critical switching nodes of the circuits. In this way, both latency andpower consumption of pulse triggered flip-flops are reduced. The proposed approach is assessed bymeans of simulations in 90-nm ST commercial CMOS technology. When applied to some recentlyproposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speedto be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also theprocess variation tolerance is considerably improved.
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops / Lanuzza, Marco. - In: JOURNAL OF LOW POWER ELECTRONICS. - ISSN 1546-1998. - 9:4(2013).
Scheda prodotto non validato
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo
| Titolo: | A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops |
| Autori: | |
| Data di pubblicazione: | 2013 |
| Rivista: | |
| Citazione: | A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops / Lanuzza, Marco. - In: JOURNAL OF LOW POWER ELECTRONICS. - ISSN 1546-1998. - 9:4(2013). |
| Handle: | http://hdl.handle.net/20.500.11770/135541 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
File in questo prodotto:
http://hdl.handle.net/20.500.11770/135541
Copyright © 2021