A new time-domain model that enables loss effects on the input impedance of on-chip transmission lines during switching transients to be accurately taken into account is presented. The model has been specifically developed for use in conjunction with MOS macromodels to predict the electrical behaviour of matched CMOS buffers. It solves the problem of mixed frequency/time domain analysis by replacing the lines with a lumped time-varying resistor.

Time-domain macromodel for lossy VLSI interconnects

CAPPUCCINO, Gregorio;COCORULLO, Giuseppe
2000

Abstract

A new time-domain model that enables loss effects on the input impedance of on-chip transmission lines during switching transients to be accurately taken into account is presented. The model has been specifically developed for use in conjunction with MOS macromodels to predict the electrical behaviour of matched CMOS buffers. It solves the problem of mixed frequency/time domain analysis by replacing the lines with a lumped time-varying resistor.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11770/136235
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