This short note describes a new high performance combined division/square root unit. The architecture is based on a pipelined cellular array. Carry select adders are used in order to improve performance. The proposed implementation avoids latency cycles during operation mode changes. Moreover, non-redundant arithmetic is used and, therefore, no additional conversion circuitry is required.

High throughput combined division square root unit

CORSONELLO, Pasquale;CAPPUCCINO, Gregorio;COCORULLO, Giuseppe
1998-01-01

Abstract

This short note describes a new high performance combined division/square root unit. The architecture is based on a pipelined cellular array. Carry select adders are used in order to improve performance. The proposed implementation avoids latency cycles during operation mode changes. Moreover, non-redundant arithmetic is used and, therefore, no additional conversion circuitry is required.
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/141728
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 1
social impact