This short note describes a new high performance combined division/square root unit. The architecture is based on a pipelined cellular array. Carry select adders are used in order to improve performance. The proposed implementation avoids latency cycles during operation mode changes. Moreover, non-redundant arithmetic is used and, therefore, no additional conversion circuitry is required.
High throughput combined division square root unit
CORSONELLO, Pasquale;CAPPUCCINO, Gregorio;COCORULLO, Giuseppe
1998-01-01
Abstract
This short note describes a new high performance combined division/square root unit. The architecture is based on a pipelined cellular array. Carry select adders are used in order to improve performance. The proposed implementation avoids latency cycles during operation mode changes. Moreover, non-redundant arithmetic is used and, therefore, no additional conversion circuitry is required.File in questo prodotto:
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