This paper presents the architecture and complete VLSI implementation of a high data throughput, energy and area efficient data path targeted for DSP and multimedia applications. The architecture presented here is extremely flexible and can be easily extended to process 8-16-32 bit operands. For the initial analysis and design, three different implementations of the reconfigurable data path using static, dynamic domino and D3L logic styles were implemented to evaluate the performance of the proposed architecture in static as well as dynamic design domains. This paper presents complete evaluations of the architecture, along with an analysis of every design decision from the lowermost level. The proposed architecture can be easily extended to generalized N-bit operations. This is demonstrated through the custom implementation of 8-16 and 32 bit versions.
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|Titolo:||Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems|
|Data di pubblicazione:||2009|
|Citazione:||Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems / Purhoit, S; Lanuzza, Marco; Perri, Stefania; Corsonello, Pasquale; Margala, M.. - In: JOURNAL OF LOW POWER ELECTRONICS. - ISSN 1546-1998. - 5:3(2009), pp. 326-338.|
|Appare nelle tipologie:||1.1 Articolo in rivista|