This paper presents a novel stereo matching algorithm that synergistically exploits in an original way the Adaptive Census Transform and the Support Local Binary Pattern approaches. For the first time, the Support Local Binary Pattern technique is applied to efficiently process large windows of pixels without excessive computational requirements, and thus allowing easy design of specific integrated circuits. Results obtained for conventional benchmark image sets demonstrate that, despite the simplifications adopted to make the novel algorithm hardware-friendly, the method proposed here can reach qualities higher than its competitors. Several hardware implementations have been carried out and characterized on the Xilinx Virtex FPGA chips. For 640 × 480 stereo images and a disparity range equal to 60, the proposed architecture guarantees an average error in computing the map as low as 9% with a throughput rate up to 68 frames per second. The cheapest version of a system designed as reported in this paper occupies less than 49,000 slices, 112 DSPs and 32 BRAMs.

An Efficient Hardware-Oriented Stereo Matching Algorithm

Cocorullo G;CORSONELLO, Pasquale;Frustaci F;PERRI, Stefania
2016

Abstract

This paper presents a novel stereo matching algorithm that synergistically exploits in an original way the Adaptive Census Transform and the Support Local Binary Pattern approaches. For the first time, the Support Local Binary Pattern technique is applied to efficiently process large windows of pixels without excessive computational requirements, and thus allowing easy design of specific integrated circuits. Results obtained for conventional benchmark image sets demonstrate that, despite the simplifications adopted to make the novel algorithm hardware-friendly, the method proposed here can reach qualities higher than its competitors. Several hardware implementations have been carried out and characterized on the Xilinx Virtex FPGA chips. For 640 × 480 stereo images and a disparity range equal to 60, the proposed architecture guarantees an average error in computing the map as low as 9% with a throughput rate up to 68 frames per second. The cheapest version of a system designed as reported in this paper occupies less than 49,000 slices, 112 DSPs and 32 BRAMs.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/143295
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