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EnglishThis brief deals with a new design of low-power SRAM wordline decoder in the 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. The proposed approach synergistically adopts the poly biasing technique in conjunction with single-well/flip-well configurations and body biasing to opportunely tune the threshold voltage of the devices in the standby and active mode. A tuning methodology is described to optimize the static energy consumption. Post-layout simulations, done at power supply voltages ranging between 1 V and 0.5 V, have shown that, in comparison with the state-of-the-art techniques based on the same UTBB FDSOI technology, the proposed design achieves a maximum leakage up to 85% lower without paying significant delay penaltie
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology / Corsonello, Pasquale; Frustaci, F; Perri, Stefania. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 23:12(2015), pp. 3133-3137.
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| Titolo: | Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology |
| Autori: | |
| Data di pubblicazione: | 2015 |
| Rivista: | |
| Citazione: | Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology / Corsonello, Pasquale; Frustaci, F; Perri, Stefania. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 23:12(2015), pp. 3133-3137. |
| Handle: | http://hdl.handle.net/20.500.11770/144466 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
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