Analytical model for the 1/f noise in the tunneling current through metal-oxide-semiconductor structures

In this paper we propose an analytical model for the 1/f noise in the tunneling current through metal-oxide-semiconductor structures. The 1/f noise is ascribed to the superimposition of random telegraph signals due to elastic electron tunneling from the inversion layer to oxide traps and vice versa. The model is based on the observation that an electron trapped in the dielectric locally increases the potential barrier thus reducing the current density. The local reduction in the current density is described in terms of an effective blocking area where the current density is null when the electron is trapped. The radius of the blocking area depends smoothly on the trap spatial position and on the applied voltage, and it is roughly equal to half of the oxide thickness. Detrapping to the gate is not considered. Numerical simulations show that it is important only in a thin intermediate region inside the oxide and that the corresponding power contribution is negligible respect to that generated by traps closer to the substrate interface. The model allows us to extract an effective trap density inside the dielectric as a function of the Fermi energy from current 1/f noise measurements for different bias voltages. Trap densities in the order of 10(20) cm(-3) eV(-1) are obtained from 1/f noise measurements carried on SiO(2)/polysilicon gate n-metal-oxide-semiconductor-field-effect-transistors (nMOSFETs) which are in agreement with values already reported by previous works. Experiments have confirmed the area, frequency, and bias dependence of the gate current noise predicted by the proposed model.

In this paper we propose an analytical model for the 1/f noise in the tunneling current through metal-oxide-semiconductor structures. The 1/f noise is ascribed to the superimposition of random telegraph signals due to elastic electron tunneling from the inversion layer to oxide traps and vice versa. The model is based on the observation that an electron trapped in the dielectric locally increases the potential barrier thus reducing the current density. The local reduction in the current density is described in terms of an effective blocking area where the current density is null when the electron is trapped. The radius of the blocking area depends smoothly on the trap spatial position and on the applied voltage, and it is roughly equal to half of the oxide thickness. Detrapping to the gate is not considered. Numerical simulations show that it is important only in a thin intermediate region inside the oxide and that the corresponding power contribution is negligible respect to that generated by traps closer to the substrate interface. The model allows us to extract an effective trap density inside the dielectric as a function of the Fermi energy from current 1/f noise measurements for different bias voltages. Trap densities in the order of 10(20) cm(-3) eV(-1) are obtained from 1/f noise measurements carried on SiO(2)/polysilicon gate n-metal-oxide-semiconductor-field-effect-transistors (nMOSFETs) which are in agreement with values already reported by previous works. Experiments have confirmed the area, frequency, and bias dependence of the gate current noise predicted by the proposed model. (c) 2009 American Institute of Physics. [doi:10.1063/1.3236637]