A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed, avoiding time-consuming trial-anderror design processes. A design example in 0.35 mm CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.
Settling Time Optimisation for Two-Stage CMOS Amplifiers With Current-Buffer Miller Compensation
CAPPUCCINO, Gregorio;COCORULLO G.
2007-01-01
Abstract
A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed, avoiding time-consuming trial-anderror design processes. A design example in 0.35 mm CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.File in questo prodotto:
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