The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (Sigma Delta M) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35 mu m CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in Sigma Delta M behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase. (C) 2010 Elsevier Ltd. All rights reserved.
Analysis of op-amp phase margin impact on SC Sigma Delta modulator performance
CAPPUCCINO, Gregorio;COCORULLO, Giuseppe
2010-01-01
Abstract
The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (Sigma Delta M) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35 mu m CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in Sigma Delta M behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase. (C) 2010 Elsevier Ltd. All rights reserved.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
