Data Driven Dynamic Logic (D3L) achieves a considerably energy saving, over conventional Domino Logic, by removing the clock signal: the control of the precharge and evaluation phases is managed only by input data. Unfortunately, this advantage is typically obtained at the expense of speed performances and consequently affecting the Energy-Delay Product (EDP). This paper presents a novel technique to design D3L parallel prefix adders considerably reducing speed penalties. Moreover, a new design style, named Splith-Path D3L, is introduced to overcome the limits of standard D3L. When applied to a 32-bit Kogge-Stone adder realized with the STMicroelectronics 65nm 1V CMOS technology, the proposed technique leads to an EDP 25% and 20% lower than the standard Domino Logic and the conventional D3L counterparts, respectively.
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