In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.
Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI
TACO R;LANUZZA, Marco;
2015-01-01
Abstract
In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology, is proposed. The circuit synergistically benefits from low-granularity back-bias control to improve performance in conjunction with the integration of both NMOS and PMOS devices into a common well configuration which allows highly efficient area utilization. The design was compared over standard CMOS and DTMOS solutions. Comparative post-layout results demonstrate that the suggested approach improves energy consumption up to 57% in comparison to the equivalent DTMOS design and reduces delay up to 30% with similar energy consumption, when compared to the conventional CMOS implementation. In addition, reduced silicon area occupancy is achieved.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
