This paper presents a novel Connected Component Analysis hardware architecture suitable for high-performance heterogeneous image processing embedded systems. The target application referenced along the work is the Automated Traffic Sign Recognition for next generation Advanced Driver-Assistance Systems. In such a field, a high throughput rate is mandatory to obey high-speed camera input frame rate. The proposed architecture executes a complete Connected Component Analysis by just one scan of the input image; therefore, it reaches performances higher than several existing hardware designs. When implemented on a Xilinx Zynq Z7045 SoC, our design allows a throughput rate of 212 Mpixels/s to be reached using 18144 LUTs and 5005 FFs, which correspond to less than 9% and 1.5% of the available resources.
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems
Spagnolo, Fanny;Perri, Stefania;Frustaci, Fabio;Corsonello, Pasquale
2019-01-01
Abstract
This paper presents a novel Connected Component Analysis hardware architecture suitable for high-performance heterogeneous image processing embedded systems. The target application referenced along the work is the Automated Traffic Sign Recognition for next generation Advanced Driver-Assistance Systems. In such a field, a high throughput rate is mandatory to obey high-speed camera input frame rate. The proposed architecture executes a complete Connected Component Analysis by just one scan of the input image; therefore, it reaches performances higher than several existing hardware designs. When implemented on a Xilinx Zynq Z7045 SoC, our design allows a throughput rate of 212 Mpixels/s to be reached using 18144 LUTs and 5005 FFs, which correspond to less than 9% and 1.5% of the available resources.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
