Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip

The image convolution is a crucial task in several computer vision applications. Modern Convolutional Neural Networks (CNNs) involve 2D convolution filters of different sizes over a set of input images with various resolutions. Unfortunately, state-of-the-art hardware accelerators do not well fit the radical variations that may occur within a CNN algorithm. This paper presents a novel reconfigurable convolution architecture purposely designed to support runtime variable kernel and image sizes. Results, obtained by integrating the proposed accelerator within a Zynq Ultrascale-based embedded system targeted for inference of CNNs, show that significantly higher performance-resource and performance-power efficiencies are reached in comparison with several existing hardware designs.