The image convolution is a crucial task in several computer vision applications. Modern Convolutional Neural Networks (CNNs) involve 2D convolution filters of different sizes over a set of input images with various resolutions. Unfortunately, state-of-the-art hardware accelerators do not well fit the radical variations that may occur within a CNN algorithm. This paper presents a novel reconfigurable convolution architecture purposely designed to support runtime variable kernel and image sizes. Results, obtained by integrating the proposed accelerator within a Zynq Ultrascale-based embedded system targeted for inference of CNNs, show that significantly higher performance-resource and performance-power efficiencies are reached in comparison with several existing hardware designs.

Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip

Spagnolo F.;Perri S.;Frustaci F.;Corsonello P.
2020-01-01

Abstract

The image convolution is a crucial task in several computer vision applications. Modern Convolutional Neural Networks (CNNs) involve 2D convolution filters of different sizes over a set of input images with various resolutions. Unfortunately, state-of-the-art hardware accelerators do not well fit the radical variations that may occur within a CNN algorithm. This paper presents a novel reconfigurable convolution architecture purposely designed to support runtime variable kernel and image sizes. Results, obtained by integrating the proposed accelerator within a Zynq Ultrascale-based embedded system targeted for inference of CNNs, show that significantly higher performance-resource and performance-power efficiencies are reached in comparison with several existing hardware designs.
2020
978-1-7281-6949-1
embedded systems
FPGA
image convolution
reconfigurable design
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/314983
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