Object detection represents one of the most important and challenging task in computer vision applications. Boosting-based approaches deal with computational intensive operations and they involve several sequential tasks that make very difficult developing hardware implementations with high parallelism level. This work presents a new hardware architecture able to perform object detection based on a cascade classifier in real-time and resource-constrained systems. As case study, the proposed architecture has been tailored to accomplish the face detection task and integrated within a complete heterogeneous embedded system based on a Xilinx Zynq-7000 FPGA-based System-on-Chip. Experimental results show that, thanks to the proposed parallel processing scheme and the runtime adaptable strategy to slide sub-windows across the input image, the novel design achieves a frame rate up to 125fps for the QVGA resolution, thus significantly outperforming previous works. Such a performance is obtained by using less than 10% of on-chip available logic resources with a power consumption of 377 mW at the 100 MHz clock frequency.
Design of a real-time face detection architecture for heterogeneous systems-on-chips
Spagnolo F.;Perri S.;Corsonello P.
2020-01-01
Abstract
Object detection represents one of the most important and challenging task in computer vision applications. Boosting-based approaches deal with computational intensive operations and they involve several sequential tasks that make very difficult developing hardware implementations with high parallelism level. This work presents a new hardware architecture able to perform object detection based on a cascade classifier in real-time and resource-constrained systems. As case study, the proposed architecture has been tailored to accomplish the face detection task and integrated within a complete heterogeneous embedded system based on a Xilinx Zynq-7000 FPGA-based System-on-Chip. Experimental results show that, thanks to the proposed parallel processing scheme and the runtime adaptable strategy to slide sub-windows across the input image, the novel design achieves a frame rate up to 125fps for the QVGA resolution, thus significantly outperforming previous works. Such a performance is obtained by using less than 10% of on-chip available logic resources with a power consumption of 377 mW at the 100 MHz clock frequency.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
