This paper presents a power-efficient hardware architecture designed to perform 3D convolution operations in modern high-performance FPGA-based video processors. The proposed design exploits a novel platform-independent Single-Instruction-Multiple-Data modality to process input data, thus allowing multiple levels of parallelism to be supported. For purposes of comparison with existing hardware accelerators, several implementations are characterized using different FPGA devices. When accommodated within low-end chips, such as the Xilinx XC7Z020, the proposed convolution engine exhibits a maximum clock frequency 22% higher than the competitors, without significantly increasing the dynamic energy consumption. When more advanced DSP slices are used, like those available in Xilinx Ultrascale FPGA devices the proposed convolution engine dissipates up to 40% less dynamic energy than existing counterparts, without significant speed performance penalties.
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