This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from − 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.
Live Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths
Taco R.;Lanuzza M.;
2021-01-01
Abstract
This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from − 40 ° C to 125 ° C confirmed the effectiveness of the proposed approach to compensate even for severe process, voltage and temperature (PVT) variations.File in questo prodotto:
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