A Hardware-Aware Methodology for Distributed In-Network Intelligence on FPGA-Based SmartNICs

Future network infrastructures will increasingly leverage artificial intelligence (AI) models for automation of internal management procedures and for service offering. To this aim, distributing learning capabilities within Programmable Data Planes (PDPs) can offer clear advantages, but at the cost of complex design challenges. In this paper, we introduce an effective methodology for distributing AI capabilities across PDP devices, considering hardware resource utilization and energy consumption. Experimental evaluations conducted on FPGA-based programmable platforms demonstrate that the proposed design, when applied to anomalous network traffic detection, attains very high precision, high throughput, and improved power efficiency compared to state-of-the-art solutions in the literature.