GARZON CORDOVA, ESTEBAN JOSE

GARZON CORDOVA, ESTEBAN JOSE  

Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica  

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Risultati 1 - 20 di 30 (tempo di esecuzione: 0.066 secondi).
Titolo Data di pubblicazione Autore(i) File
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1-gen-2022 Zambrano, Benjamin; Garzon, Esteban; Strangio, S.; Crupi, F.; Lanuzza, M.
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion 1-gen-2022 Zambrano, Benjamin.; Garzon, Esteban; Strangio, S.; Iannaccone, G.; Lanuzza, M.
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 1-gen-2022 Garzon, Esteban; De Rose, R.; Crupi, F.; Trojman, L.; Teman, A.; Lanuzza, M.
AIDA: Associative In-memory Deep learning Accelerator 1-gen-2022 Garzon, Esteban; Teman, A.; Lanuzza, M.; Yavits, L.
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification 1-gen-2022 Zambrano, Benjamin; Strangio, S.; Rizzo, T.; Garzon, Esteban; Lanuzza, M.; Iannaccone, G.
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 1-gen-2019 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Lanuzza, M.
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 1-gen-2020 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Finocchio, G.; Carpentieri, M.; Lanuzza, M.
Capacitance Extraction of 34-nm Metallurgical Channel Length MOSFET for Parasitic Assessment Using the RFCV Technique 1-gen-2018 Benalcazar, D. R.; Garzon, Esteban; Trojman, L.
Device-to-system level simulation framework for STT-DMTJ based cache memory 1-gen-2019 Garzon, E.; De Rose, R.; Crupi, F.; Lanuzza, M.
EDAM: Edit Distance tolerant Approximate Matching content addressable memory 1-gen-2022 Hanhan, R.; Garzon, Esteban; Jahshan, Z.; Teman, A.; Lanuzza, M.; Yavits, L.
Embedded memories for cryogenic applications 1-gen-2022 Garzon, Esteban; Teman, A.; Lanuzza, M.
Emerging Memory Structures for VLSI Circuits 1-gen-2022 Garzon, Esteban; Yavits, Leonid; Lanuzza, Marco; Teman, Adam
Energy efficient self-adaptive dual mode logic address decoder 1-gen-2021 Vicuna, K.; Mosquera, C.; Musello, A.; Benedictis, S.; Rendon, M.; Garzon, Esteban; Procel, L. M.; Trojman, L.; Taco, R.
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 1-gen-2019 Lanuzza, M.; Rose, R. D.; Garzon, E.; Crupi, F.
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs 1-gen-2019 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Finocchio, G.; Carpentieri, M.; Lanuzza, M.
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 1-gen-2021 Garzon, E.; De Rose, R.; Crupi, F.; Teman, A.; Lanuzza, M.
Fast computation of Cramer-Rao Bounds for TOA: An application to network-based positioning simulations 1-gen-2017 Garzon, Esteban; Valdiviezo, S.; Jativa, R.; Vidal, J.
Field-Free Magnetic Tunnel Junction for Logic Operations Based on Voltage-Controlled Magnetic Anisotropy 1-gen-2021 Cutugno, F.; Garzon, Esteban; De Rose, R.; Finocchio, G.; Lanuzza, M.; Carpentieri, M.
Gain-Cell Embedded DRAM Under Cryogenic Operation--A First Study 1-gen-2021 Garzon, E.; Greenblatt, Y.; Harel, O.; Lanuzza, M.; Teman, A.
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification 1-gen-2022 Garzon, Esteban; Golman, R.; Jahshan, Z.; Hanhan, R.; Vinshtok-Melnik, N.; Lanuzza, M.; Teman, A.; Yavits, L.