Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations

Wide fan-in dynamic logic gates are difficult to design due to the large number of leaky evaluation pathsconnected to the dynamic node. Designers have to cope with their low noise tolerance further worsenedby the effects of process parameter variation.In this paper, a novel analytical model is derived and validated to evaluate the noise robustness of widefan-in dynamic logic gates taking process variation effects into account. Experiments were performed usinga commercial 45-nm 1-V CMOS technology, and the noise robustness in terms of unity noise gain (UNG)was evaluated for 16 and 32-bit OR gates. Obtained results demonstrate that the proposed model is able topredict the mean value of the UNG with a maximum error of only 6.8%, whereas the difference between thepredicted and simulated UNG yield is always lower than five percentage points.