The work focuses on the impact of the finite and variable MOSFET output resistance on the transient response LC transmission line drivers. Experimental results highlight the severe error occurring in conventional timing analysis when actual finite resistance of the device is neglected. A novel analytical model is presented to capture the variable resistance of the driver. The model allows closed-form expressions for the output waveform to be carried out, and it agrees well with HSPICE simulations. The proposed model is suitable to figure fundamental timing parameters of CMOS gates driving lossless transmission lines, such as the propagation delay, transition time, as well as power estimation. (C) 2007 Wiley Periodicals, Inc.

The work focuses on the impact of the finite and variable MOSFET output resistance on the transient response LC transmission line drivers. Experimental results highlight the severe error occurring in conventional timing analysis when actual finite resistance of the device is neglected. A novel analytical model is presented to capture the variable resistance of the driver. The model allows closed-form expressions for the output waveform to be carried out, and it agrees well with HSPICE simulations. The proposed model is suitable to figure fundamental timing parameters of CMOS gates driving lossless transmission lines, such as the propagation delay, transition time, as well as power estimation. (C) 2007 Wiley Periodicals, Inc.

Impact of the variable output resistance on the transient response of LC transmission line CMOS buffers and its model

CAPPUCCINO, Gregorio;CRUPI, Felice;
2007

Abstract

The work focuses on the impact of the finite and variable MOSFET output resistance on the transient response LC transmission line drivers. Experimental results highlight the severe error occurring in conventional timing analysis when actual finite resistance of the device is neglected. A novel analytical model is presented to capture the variable resistance of the driver. The model allows closed-form expressions for the output waveform to be carried out, and it agrees well with HSPICE simulations. The proposed model is suitable to figure fundamental timing parameters of CMOS gates driving lossless transmission lines, such as the propagation delay, transition time, as well as power estimation. (C) 2007 Wiley Periodicals, Inc.
The work focuses on the impact of the finite and variable MOSFET output resistance on the transient response LC transmission line drivers. Experimental results highlight the severe error occurring in conventional timing analysis when actual finite resistance of the device is neglected. A novel analytical model is presented to capture the variable resistance of the driver. The model allows closed-form expressions for the output waveform to be carried out, and it agrees well with HSPICE simulations. The proposed model is suitable to figure fundamental timing parameters of CMOS gates driving lossless transmission lines, such as the propagation delay, transition time, as well as power estimation. (C) 2007 Wiley Periodicals, Inc.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/136807
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