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EnglishData-driven dynamic logic (D3L) is very efficient when low-power constraints are mandatory. Unfortunately, this advantage is typically obtained at the expense of speed performances. This paper presents a novel technique to realize D3L parallel prefix tree adders without significantly compromising speed performance. When applied to a 64-bit Kogge-Stone adder realized with 90-nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed technique leads to an energy-delay product that is 29% and 21% lower than its standard domino logic and conventional D3L counterparts, respectively. It also shows a worst case delay that is 10% lower than that of the D3L approach and only 5% higher than that of the conventional domino logic.
Designing High-Speed Adders in Power-Constrained Environments / Frustaci, F; Lanuzza, Marco; Zicari, P; Perri, Stefania; Corsonello, Pasquale. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 56:2(2009), pp. 172-176.
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| Titolo: | Designing High-Speed Adders in Power-Constrained Environments |
| Autori: | |
| Data di pubblicazione: | 2009 |
| Rivista: | |
| Citazione: | Designing High-Speed Adders in Power-Constrained Environments / Frustaci, F; Lanuzza, Marco; Zicari, P; Perri, Stefania; Corsonello, Pasquale. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - 56:2(2009), pp. 172-176. |
| Handle: | http://hdl.handle.net/20.500.11770/141716 |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
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