A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5?GHz maximum running frequency and 0.77 mu W/ MHz energy dissipation. Copyright (C) 2010 John Wiley & Sons, Ltd.
A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5?GHz maximum running frequency and 0.77 mu W/ MHz energy dissipation. Copyright (C) 2010 John Wiley & Sons, Ltd.
Energy-efficient single-clock-cycle binary comparator
Frustaci Fabio;PERRI, Stefania;LANUZZA, Marco;CORSONELLO, Pasquale
2012-01-01
Abstract
A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5?GHz maximum running frequency and 0.77 mu W/ MHz energy dissipation. Copyright (C) 2010 John Wiley & Sons, Ltd.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.