Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 x 16 bit Booth multiplier realised with STMicroelectronics 65 nm 1V CMOS technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively.
Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 x 16 bit Booth multiplier realised with STMicroelectronics 65 nm 1V CMOS technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively.
Low-power split-path data-driven dynamic logic
Frustaci F.;LANUZZA, Marco;PERRI, Stefania;CORSONELLO, Pasquale
2009-01-01
Abstract
Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 x 16 bit Booth multiplier realised with STMicroelectronics 65 nm 1V CMOS technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
