Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework

In this paper, we focus on the study of the impact of voltage scaling on writing performance and energy of STT-MRAM arrays featuring four different configurations of bitcell. The memory arrays are implemented by a circular MTJ with a diameter of 30 nm and a 28-nm UTBB FDSOI CMOS technology. The analysis is performed by considering the effect of both CMOS and MTJ process variations, and the stochastic variations of the MTJ switching time. The MTJ behavior is integrated into a commercial circuit design tool in the form of a Verilog-A LUT-based code, which exploits as inputs the outcomes of micromagnetic multi-domain simulations to ensure more accurate modeling of the MTJ characteristics. Simulation results show that the write performance and energy of STT-MRAMs strongly depend on the bitcell configuration. The energy saving achieved through voltage scaling is found to be up to 37% at the cost of a delay penalty of 3.3×, as compared to the write operation at the nominal voltage of 1 V.