This paper focuses on the design of a 3-transistor (3T) current reference, which allows sub-1-V nanopower operation. The impact of the basic electrical and geometrical parameters of the three transistors on circuit performance is discussed by means of simulations in a commercial 0.18 μm CMOS technology. We also report experimental results on a test chip, which are consistent with the simulation predictions. When compared to state-of-the-art nanopower competitors, the fabricated circuit proves to be a competitive candidate thanks to the very low minimum operating voltage (0.45 V) and small area occupation (only 750 μm2), while exhibiting competitive performance in terms of temperature coefficient (578 ppm/°C) and power consumption (213 nW).
Design of a 3T current reference for low-voltage, low-power operation
De Rose, Raffaele;Crupi, Felice;PALIY, MAKSYM;Lanuzza, Marco;
2018-01-01
Abstract
This paper focuses on the design of a 3-transistor (3T) current reference, which allows sub-1-V nanopower operation. The impact of the basic electrical and geometrical parameters of the three transistors on circuit performance is discussed by means of simulations in a commercial 0.18 μm CMOS technology. We also report experimental results on a test chip, which are consistent with the simulation predictions. When compared to state-of-the-art nanopower competitors, the fabricated circuit proves to be a competitive candidate thanks to the very low minimum operating voltage (0.45 V) and small area occupation (only 750 μm2), while exhibiting competitive performance in terms of temperature coefficient (578 ppm/°C) and power consumption (213 nW).I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
