—In the last few years, binary comparators have received a great deal of attention as parts of complex computational data-paths. However, while several multi-bit architectures have been demonstrated using conventional CMOS technologies, few examples of n-bit comparators, with n higher than 4, can be found in literature for designs based on emerging nanotechnologies, such as the Quantum Dot Cellular Automata, the Nano Magnetic Logic, and many others. This paper proposes a novel approach to design efficient multi-bit binary comparators using the Quantum Dot Cellular Automata nanotechnology. The approach here presented allows improving state-of-the-art competitors in terms of computational complexity and average energy consumption. As an example, in comparison with its direct counterparts, the 32-bit comparator designed as proposed here saves up to 26%, 23% and 11% of the occupied area, the used basic cells and the average energy consumption, respectively. When implemented using the Nano Magnetic Logic, the 4-bit version of the novel comparator uses 1183 magnets and 38 clock phases
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