This letter presents a novel leading zero counter (LZC) able to efficiently exploits the hardware resources available within state-of-the-art FPGA devices to achieve high speed performances with limited energy consumption. Postimplementation results, obtained for operands bit-widths varying between 4-and 64-bit, demonstrate that the new design improves its direct competitors in terms of occupied lookup tables (LUTs), power consumption and computational speed. As an example, when implemented using the Xilinx Artix-7 xc7a100tcsg324 device, the new 64-bit LZC utilizes up to 36% less LUTs, dissipates up to 2.8 times lower power and is up to 20% faster than state-ofthe-art counterparts

Design of Leading Zero Counters on FPGAs

Perri, Stefania
;
Spagnolo, Fanny;Frustaci, Fabio;Corsonello, Pasquale
2022-01-01

Abstract

This letter presents a novel leading zero counter (LZC) able to efficiently exploits the hardware resources available within state-of-the-art FPGA devices to achieve high speed performances with limited energy consumption. Postimplementation results, obtained for operands bit-widths varying between 4-and 64-bit, demonstrate that the new design improves its direct competitors in terms of occupied lookup tables (LUTs), power consumption and computational speed. As an example, when implemented using the Xilinx Artix-7 xc7a100tcsg324 device, the new 64-bit LZC utilizes up to 36% less LUTs, dissipates up to 2.8 times lower power and is up to 20% faster than state-ofthe-art counterparts
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/341619
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