Sfoglia per Autore
VLSI implementation of low-power high-speed self-timed adder
2000-01-01 Corsonello, Pasquale; Perri, S.; Cocorullo, G.
VLSI implementation of a low-power high-speed self-timed adder
2000-01-01 Corsonello, Pasquale; Perri, Stefania; Cocorullo, G.
Tradeoffs in Digital Binary Adder Design: the effects of floorplanning, number of levels of metals, and supply voltage on performance and area
2001-01-01 V., Kantabutra; Perri, Stefania; Corsonello, Pasquale
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing
2001-01-01 Cappuccino, G.; Cocorullo, G.; Corsonello, Pasquale; Perri, Stefania; Staino, G.
Tradeoff in digital binary adder design: the effects of floorplanning, number of levels of metals and supply voltage on performance and area
2001-01-01 Kantabutra, V.; Corsonello, Pasquale; Perri, S.
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines
2001-01-01 G., Cappuccino; Corsonello, Pasquale; Cocorullo, Giuseppe; Perri, Stefania; G., Staino
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines
2001-01-01 Cappuccino, Gregorio; Corsonell, P.; Cocorullo, G.; Perri, S.; Staino, G.
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits
2001-01-01 Perri, Stefania; Corsonello, Pasquale; Cocorullo, Giuseppe; Cappuccino, Gregorio; Staino, G.
Efficient, Practical Adders for FPGAs
2002-01-01 Kantabutra, V; Corsonello, Pasquale; Perri, Stefania; Iachino, M. A.
Adders and Bit Blocks having an internal propagation characteristic independent of a carry input to the bit block and methods for using the same
2002-01-01 Kantabutra, V.; Corsonello, Pasquale; Perri, Stefania
ADDERS AND ADDER BIT BLOCKS HAVING AN INTERNAL PROPAGATION CHARACTERISTIC INDEPENDENT OF A CARRY INPUT TO THE BIT BLOCK AND METHODS FOR USING THE SAME
2002-01-01 Kantabutra, V.; Corsonello, Pasquale; Perri, S.
64-bit reconfigurable adder for low power media processing
2002-01-01 Perri, Stefania; Corsonello, Pasquale; Cocorullo, Giuseppe
Speed-efficient wide adders for Virtex FPGAs
2002-01-01 Perri, Stefania; M. A., Iachino; Corsonello, Pasquale
Efficient implementation of cellular algorithms on reconfigurable hardware
2002-01-01 Corsonello, Pasquale; G., Spezzano; G., Staino; Talia, Domenico
VLSI circuits for low-power high-speed asynchronous addition
2002-01-01 Perri, Stefania; Corsonello, Pasquale; Cocorullo, Giuseppe
Moltiplicatore riconfigurabile 16bx16b su FPGA Xilinx
2003-01-01 Iachino, 1. 7. M. A.; Perri, Stefania; Corsonello, P.
Power Factor Correction in Single-phase Rectifiers: a Comparative Performance Analysis of Passive and Active Line-frequency-commutated Power Supplies
2003-01-01 R., Carbone; A., Scappatura; M., Fantauzzi; Corsonello, Pasquale
SIMD 2-D Convolver for Fast FPGA-based Image and Video Processors
2003-01-01 Perri, Stefania; Lanuzza, M.; Corsonello, Pasquale; Cocorullo, G.
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors
2003-01-01 Perri, Stefania; Lanuzza, M.; Corsonello, Pasquale; Cocorullo, G.
Moltiplicatore riconfigurabile 32bx32b basato su macro Xilinx
2003-01-01 Iachino, 1. 6. M. A.; Pirrello, F.; Perri, Stefania; Corsonello, P.
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