In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUFs) is presented. The proposed solution exploits the variability of a simple voltage divider, implemented by two identical series-connected nMOSFETs in a commercial 65-nm CMOS process, to generate a random and stable nanokey. Both the transistors are biased in the subthreshold regime to enhance the output voltage dispersion and consequently the variability of the PUF response. The bit key generation is obtained by comparing the analog outputs of a pair of voltage dividers. Monte Carlo simulations on 10,000 samples have been performed to deduce the design guidelines for transistor sizing aimed at ensuring a high robustness of the PUF response against noise, supply voltage, and temperature variations. When compared with some state-of-the-art PUF designs, the proposed circuit solution proves to be a promising and competitive candidate for implementing analog and static PUFs featuring small area occupancy, low-power features, and high reliability.

A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider

De Rose R;CRUPI, Felice;LANUZZA, Marco;
2017

Abstract

In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUFs) is presented. The proposed solution exploits the variability of a simple voltage divider, implemented by two identical series-connected nMOSFETs in a commercial 65-nm CMOS process, to generate a random and stable nanokey. Both the transistors are biased in the subthreshold regime to enhance the output voltage dispersion and consequently the variability of the PUF response. The bit key generation is obtained by comparing the analog outputs of a pair of voltage dividers. Monte Carlo simulations on 10,000 samples have been performed to deduce the design guidelines for transistor sizing aimed at ensuring a high robustness of the PUF response against noise, supply voltage, and temperature variations. When compared with some state-of-the-art PUF designs, the proposed circuit solution proves to be a promising and competitive candidate for implementing analog and static PUFs featuring small area occupancy, low-power features, and high reliability.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11770/132885
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