Magnetic tunnel junctions (MTJs) are attracting an increasing interest due to their potentiality for high-density nonvolatile memories. However, some issues need to be opportunely considered in the design and optimization of hybrid MTJ/CMOS circuits, such as the stochastic nature of the MTJ switching, the high write energy consumption and the susceptibility to process variations. In this paper, we evaluate the impact of both MTJ and CMOS variability on the performance of basic hybrid MTJ/CMOS circuits in state-of-the-art nanoscale technologies. To this purpose, we exploit a simulation framework combining micromagnetic and electrical simulations. Full micromagnetic simulations are used to predict the MTJ behavior in terms of magnetoresistance-current hysteresis loop and statistical distribution of the switching delay as a function of the applied current. Those data are used to set up a look-up-table-based MTJ Verilog-A model to be used in commercial electrical simulators. Considering an MTJ with a diameter of 30 nm and a 28-nm fully-depleted silicon-on-insulator CMOS technology, we have exploited the above simulation framework to perform a variability-aware analysis on the write operation of a 1-MTJ writing circuit for nonvolatile flip-flops and a 256 × 256 STT-MRAM array. Our results show that the voltage scaling can be a promising approach for energy minimization in hybrid MTJ/CMOS circuits at the expense of larger area.

Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework

De Rose R;LANUZZA, Marco;CRUPI, Felice;
2017

Abstract

Magnetic tunnel junctions (MTJs) are attracting an increasing interest due to their potentiality for high-density nonvolatile memories. However, some issues need to be opportunely considered in the design and optimization of hybrid MTJ/CMOS circuits, such as the stochastic nature of the MTJ switching, the high write energy consumption and the susceptibility to process variations. In this paper, we evaluate the impact of both MTJ and CMOS variability on the performance of basic hybrid MTJ/CMOS circuits in state-of-the-art nanoscale technologies. To this purpose, we exploit a simulation framework combining micromagnetic and electrical simulations. Full micromagnetic simulations are used to predict the MTJ behavior in terms of magnetoresistance-current hysteresis loop and statistical distribution of the switching delay as a function of the applied current. Those data are used to set up a look-up-table-based MTJ Verilog-A model to be used in commercial electrical simulators. Considering an MTJ with a diameter of 30 nm and a 28-nm fully-depleted silicon-on-insulator CMOS technology, we have exploited the above simulation framework to perform a variability-aware analysis on the write operation of a 1-MTJ writing circuit for nonvolatile flip-flops and a 256 × 256 STT-MRAM array. Our results show that the voltage scaling can be a promising approach for energy minimization in hybrid MTJ/CMOS circuits at the expense of larger area.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/132886
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