Multi-supply voltage systems on chip have been widely explored for energy-efficient elaborations. A main challenge of multi-supply voltage designs is the interfacing of digital signals coming from ultra-low-voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay-efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single-stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull-up network on the basis of the occurring transition. A test chip was fabricated in 180nm complementary metal-oxide-semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100mV of input voltages to 1.8V, while assuring an average propagation delay of about 26ns, an average static power of 100pW, and an energy per transition of 140fJ for the target voltage-level conversion from 0.4 to 1.8V.

Low energy/delay overhead level shifter for wide-range voltage conversion

LANUZZA, Marco;CRUPI F;DE ROSE R;
2017

Abstract

Multi-supply voltage systems on chip have been widely explored for energy-efficient elaborations. A main challenge of multi-supply voltage designs is the interfacing of digital signals coming from ultra-low-voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay-efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single-stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull-up network on the basis of the occurring transition. A test chip was fabricated in 180nm complementary metal-oxide-semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100mV of input voltages to 1.8V, while assuring an average propagation delay of about 26ns, an average static power of 100pW, and an energy per transition of 140fJ for the target voltage-level conversion from 0.4 to 1.8V.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11770/146842
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