This work proposes a new class of current references based on only 3 transistors that allows sub-0.5 V operation. The circuit consists of a 2-transistor block that generates a proportional-to-absolute-temperature or a complementary-to-absolute-temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal-oxide-semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal-oxide-semiconductor process. As compared to the state-of-art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm2). In spite of the extremely reduced silicon area, the fabricated chips exhibit low-process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.

A portable class of 3-transistor current references with low-power sub-0.5 V operation

Crupi, Felice;De Rose, Raffaele;Lanuzza, Marco;
2018

Abstract

This work proposes a new class of current references based on only 3 transistors that allows sub-0.5 V operation. The circuit consists of a 2-transistor block that generates a proportional-to-absolute-temperature or a complementary-to-absolute-temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal-oxide-semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal-oxide-semiconductor process. As compared to the state-of-art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm2). In spite of the extremely reduced silicon area, the fabricated chips exhibit low-process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.
CMOS analog design; Current reference; Internet of things (IoT); Low-power; Low-voltage; Electronic, Optical and Magnetic Materials; Computer Science Applications1707 Computer Vision and Pattern Recognition; Electrical and Electronic Engineering; Applied Mathematics
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/275673
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