Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers

This paper shows the steps to set up a simulation framework for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) with double-barrier and two antiparallel reference layers (DMTJs). The approach is based on a Verilog-A analytical compact model that properly takes into account the effect of the DMTJ physical stack on both resistance and statistical switching characteristics. Validation results demonstrate a good agreement of analytical calculations with both numerical simulations and experimental data. To test the functionality of the developed Verilog-A code in hybrid CMOS/STT-MTJ circuit simulations, we have investigated the performance of a non-volatile flip-flop (NVFF) implemented with DMTJs and FinFETs in comparison with its single-barrier MTJ (SMTJ)-based counterpart. The reduced switching current of DMTJs allows reducing the backup time and energy by a factor of 3X and 6.1X, respectively. Such benefits are obtained along with smaller area occupation and better performance in the flip-flop (FF) active operation mode.