In this paper, a current reference is proposed to introduce the new capability of operating under wide supply voltage ranges and at near-100% power utilization, as useful in resource-constrained systems such as IoT sensor nodes. Operation from near-threshold (0.6 V) to nominal voltage (1.8 V) is demonstrated. The proposed reference uniquely limits the power absorbed by the peripheral circuitry to only 0.1% of the overall power, thus utilizing 99.9% of it for the intended output current. As demonstrated in a 180-nm testchip (15 tested dice from the same manufacturing lot), the near-100% power utilization with its compact area of 4,000 μm2 allows power-and area-frugal reference current generation. At the system level, the low power and area cost allows to significantly scale up the number of instances within the same chip. This also enables more local reference generation as opposed to conventional references with centralized and shared periphery, shortening its distance from the output current delivery and hence simplifying the design aspects related to reference distribution (e.g., across-die process gradients, coupling noise).

A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization

Fassio L.;De Rose R.;Lanuzza M.;Crupi F.;
2021

Abstract

In this paper, a current reference is proposed to introduce the new capability of operating under wide supply voltage ranges and at near-100% power utilization, as useful in resource-constrained systems such as IoT sensor nodes. Operation from near-threshold (0.6 V) to nominal voltage (1.8 V) is demonstrated. The proposed reference uniquely limits the power absorbed by the peripheral circuitry to only 0.1% of the overall power, thus utilizing 99.9% of it for the intended output current. As demonstrated in a 180-nm testchip (15 tested dice from the same manufacturing lot), the near-100% power utilization with its compact area of 4,000 μm2 allows power-and area-frugal reference current generation. At the system level, the low power and area cost allows to significantly scale up the number of instances within the same chip. This also enables more local reference generation as opposed to conventional references with centralized and shared periphery, shortening its distance from the output current delivery and hence simplifying the design aspects related to reference distribution (e.g., across-die process gradients, coupling noise).
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11770/323186
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