This paper investigates the reliability of the 2-bit read operation under temperature variations in the Smart Material Implication (SIMPLY) Logic-in-Memory (LIM) scheme when implemented within a Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM). To be executed, such an operation requires the generation of a proper reference voltage (VREF). As a result of our study, such a VREF must take a proportional to absolute temperature (PTAT) behavior to alleviate the detrimental temperature effect on the bit error rate. Accordingly, starting from a prior art subthreshold two-transistor (2T) reference circuit, a VREF generator employing an 18T topology was designed in the adopted 65-nm CMOS technology and its effect on the reliability of the 2-bit read operation was evaluated across temperatures.
Design of a Temperature-Aware Voltage Generator for 2-Bit Read Operation in STT-MRAM Based SIMPLY Architecture
Vatalaro, Massimo;Maccaronio, Vincenzo;Crupi, Felice;Puglisi, Francesco Maria;De Rose, Raffaele
2025-01-01
Abstract
This paper investigates the reliability of the 2-bit read operation under temperature variations in the Smart Material Implication (SIMPLY) Logic-in-Memory (LIM) scheme when implemented within a Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM). To be executed, such an operation requires the generation of a proper reference voltage (VREF). As a result of our study, such a VREF must take a proportional to absolute temperature (PTAT) behavior to alleviate the detrimental temperature effect on the bit error rate. Accordingly, starting from a prior art subthreshold two-transistor (2T) reference circuit, a VREF generator employing an 18T topology was designed in the adopted 65-nm CMOS technology and its effect on the reliability of the 2-bit read operation was evaluated across temperatures.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


