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VATALARO, Massimo

VATALARO, Massimo  

Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica  

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Risultati 1 - 16 di 16 (tempo di esecuzione: 0.029 secondi).
Titolo Data di pubblicazione Autore(i) File
A Highly Reliable PUF Based on Reconfigurable Sub-Threshold Voltage Divider in 65-nm CMOS 1-gen-2026 Vatalaro, M.; De Rose, R.; Maccaronio, V.; Crupi, F.
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 1-gen-2021 Vatalaro, M.; Lanuzza, M.; Crupi, F.; Moposita, T.; Trojman, L.; Vladimirescu, A.; Strangio, S.
A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider 1-gen-2025 Vatalaro, M.; De Rose, R.; Maccaronio, V.; Lanuzza, M.; Crupi, F.
C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs 1-gen-2024 Spagnolo, F; Vatalaro, M; Perri, S; Crupi, F; Corsonello, P
Design for Reliability of Multi-Bit Operations in RRAM-Based SIMPLY Logic-in-Memory Circuits 1-gen-2025 Zanotti, Tommaso; Borellini, Erika; Vatalaro, Massimo; Maccaronio, Vincenzo; Pavan, Paolo; De Rose, Raffaele; Puglisi, Francesco Maria
Design of a Temperature-Aware Voltage Generator for 2-Bit Read Operation in STT-MRAM Based SIMPLY Architecture 1-gen-2025 Vatalaro, Massimo; Maccaronio, Vincenzo; Zanotti, Tommaso; Borellini, Erika; Crupi, Felice; Puglisi, Francesco Maria; De Rose, Raffaele
Experimental analysis of variability in WS2-based devices for hardware security 1-gen-2023 Vatalaro, M.; Neill, H.; Gity, F.; Magnone, P.; Maccaronio, V.; Marquez, C.; Galdon, J. C.; Gamiz, F.; Crupi, F.; Hurley, P.; De Rose, R.
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization 1-gen-2024 Spagnolo, Fanny; Perri, Stefania; Vatalaro, Massimo; Frustaci, Fabio; Crupi, Felice; Corsonello, Pasquale
Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations 1-gen-2025 Vatalaro, M; De Rose, R; Maccaronio, V; Lanuzza, M; Crupi, F
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions 1-gen-2019 Felicetti, Carmelo; Furfaro, Angelo; Saccà, Domenico; Vatalaro, Massimo; Lanuzza, Marco; Crupi, Felice
PUF-Based Authentication-Oriented Architecture for Identification Tags 1-gen-2025 Rullo, A.; Felicetti, C.; Vatalaro, M.; De Rose, R.; Lanuzza, M.; Crupi, F.; Sacca, D.
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider 1-gen-2022 Vatalaro, M.; De Rose, R.; Lanuzza, M.; Crupi, F.
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 1-gen-2022 Vatalaro, M.; De Rose, R.; Lanuzza, M.; Crupi, F.
Threshold Voltage Instability and Dielectric Breakdown in Flexible Bottom-Gate Ti/Al2O3/IGZO Thin-Film Transistors 1-gen-2025 De Rosis, D.; Vatalaro, M.; Maccaronio, V.; Crupi, F.; Munzenrieder, N.; Catania, F.; Corsino, D.; Cantarella, G.; Petti, L.; De Rose, R.
Threshold Voltage Instability in Flexible Bottom-Gate Al2O3/IGZO TFTs 1-gen-2024 De Rosis, D.; Vatalaro, M.; Maccaronio, V.; Crupi, F.; Munzenrieder, N.; Catania, F.; Corsino, D.; Cantarella, G.; Petti, L.; De Rose, R.
Weak Physycally Unclonable Functions in CMOS Technology: A Review 1-gen-2025 Vatalaro, Massimo; De Rose, Raffaele; Lanuzza, Marco; Crupi, Felice