This paper investigates the threshold voltage instability in flexible n-type thin film transistors (TFTs) featuring a bottom-gate Ti/Al2O3/IGZO MOS structure. Hysteresis, positive gate bias stress and negative gate bias recovery measurements were performed at room temperature on a set of 20 devices with the same channel width (W = 280 µm) and different channel length L ranging from 100 µm down to 5 µm. Both hysteresis (applying VGS from -1 V to 5 V and vice versa) and stress (applying VGS = 5 V for 1000 s) data show a positive threshold voltage shift, which can be attributed to negative charge trapping at the channel/oxide interface and/or in the bulk oxide. Moreover, the trapping rate parameter exhibits a general decreasing trend over time with values ranging from 0.28 to 0.46 in the initial stress phase and a reduction up to 88% after 1000 s of stress. Measurements also show that in most devices the stress-induced shift can be fully recovered by applying a VGS = -2 V for 1000 s as a result of releasing charges previously trapped during stress.

Threshold Voltage Instability in Flexible Bottom-Gate Al2O3/IGZO TFTs

De Rosis D.;Vatalaro M.;Maccaronio V.;Crupi F.;De Rose R.
2024-01-01

Abstract

This paper investigates the threshold voltage instability in flexible n-type thin film transistors (TFTs) featuring a bottom-gate Ti/Al2O3/IGZO MOS structure. Hysteresis, positive gate bias stress and negative gate bias recovery measurements were performed at room temperature on a set of 20 devices with the same channel width (W = 280 µm) and different channel length L ranging from 100 µm down to 5 µm. Both hysteresis (applying VGS from -1 V to 5 V and vice versa) and stress (applying VGS = 5 V for 1000 s) data show a positive threshold voltage shift, which can be attributed to negative charge trapping at the channel/oxide interface and/or in the bulk oxide. Moreover, the trapping rate parameter exhibits a general decreasing trend over time with values ranging from 0.28 to 0.46 in the initial stress phase and a reduction up to 88% after 1000 s of stress. Measurements also show that in most devices the stress-induced shift can be fully recovered by applying a VGS = -2 V for 1000 s as a result of releasing charges previously trapped during stress.
2024
hysteresis
IGZO TFTs
negative gate bias recovery
positive gate bias stress
threshold voltage instability
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11770/407078
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