Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations

This paper explores a class of highly stable staticmonostable physically unclonable functions (PUFs) based onstacked sub-threshold voltage dividers between two nominallyidentical sub-circuits as bitcell core block. More specifically,compared to our previous works where two-transistor (2T) andfour-transistor (4T) voltage divider based PUFs were presentedand analyzed, here we propose two novel topological variantsbased on six-transistor (6T) and eight-transistor (8T) solutionswhich arise from adopting a proper reverse gate-biasing strategywithin the stack with the aim of improving the resilience to on-chip noise and voltage variations, while keeping the area overheadlow. These novel solutions, along with those already proposed,were tested in 180-nm CMOS technology. Raw measurementsshow a nominal (at 1.8 V and 25degree celsius) bit error rate (BER) of0.15% and 0.08% for the 6T- and 8T-based solutions, respectively,along with a BER variation of 0.016% and 0.002% per 0.1 V.With the implementation of a simple masking technique basedon measurements at low supply voltage (VD D=0.3 V at 25degree celsius)along with a temporal majority voting (TMV) scheme, a BER of0.006% and lower than 9.77x10(-5)%, which is the minimumobservable BER for the adopted statistical set, was observed forthe 6T-, and 8T-core based implementations, respectively, witha corresponding masking ratio of 8.71% and 7.59%. This isachieved with an area per bit of 5,174F(2)(6T solution) and6,994F(2)(8T solution)