A Highly Reliable PUF Based on Reconfigurable Sub-Threshold Voltage Divider in 65-nm CMOS

This paper proposes a reconfigurable PUF bitcell based on a multi-flavor thirteen-transistor (13T) sub-threshold voltage divider as core block, interfaced with a conversion circuit for output bit generation. The reconfigurability dramatically improves the PUF stability reducing the chance of having unstable cells, while the multi-flavor approach allows for better area efficiency. The conversion circuit also generates two auxiliary voltages exploited for soft dark bit detection. In particular, a soft calibration (SC) scheme detects and corrects the unstable cells by XORing such voltages at low supply voltage (i.e., 0.4 V) and at one or more temperature points. Moreover, a hard calibration (HC) scheme is employed along with a remapping process to further enhance the PUF stability. Raw measurements in 65-nm CMOS technology show a bit error rate (BER) of 0.13% at golden key (GK) conditions (i.e., 1.0 V and 25 °C). After implementing the proposed calibration schemes (i.e., 5-point SC or HC) along with temporal majority voting (TMV), no instability at GK conditions as well as a strong BER reduction under voltage and temperature (VT) variations were achieved. Then, zero-BER under any VT condition was observed by implementing the HC scheme along with remapping and TMV. This is obtained with an area per bit of 17,042 F2, and an energy per bit of 80 fJ at a throughput of 4 Mbps.