Sfoglia per Rivista IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing
2023-01-01 Moposita, T.; Garzon, E.; Crupi, F.; Trojman, L.; Vladimirescu, A.; Lanuzza, M.
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator
2008-01-01 Perri, Stefania; Corsonello, Pasquale
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers
2022-01-01 Frustaci, Fabio; Spagnolo, Fanny; Perri, Stefania; Corsonello, Pasquale
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory
2023-01-01 Garzon, E.; Golman, R.; Lanuzza, M.; Teman, A.; Yavits, L.
Low-Power Level Shifter for Multi-Supply Voltage Designs
2012-01-01 Lanuzza, M.; Corsonello, P.; Perri, S.
Multi-Bit Full Comparator Logic in Quantum-Dot Cellular Automata
2022-01-01 Perri, S.; Spagnolo, F.; Frustaci, F.; Corsonello, P.
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter
2021-01-01 Fassio, L.; Settino, F.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths
2020-01-01 Stanger, I.; Shavit, N.; Taco, R.; Lanuzza, M.; Fish, A.
An Ultralow-Voltage Energy-Efficient Level Shifter
2017-01-01 Lanuzza, Marco; Crupi, Felice; Rao, S; DE ROSE, Raffaele; Strangio, S; Iannaccone, G.
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements
2012-01-01 Crupi, Felice; Alioto, M; Franco, J; Magnone, P; Togo, M; Horiguchi, N; Groeseneken, G.
XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs
2023-01-01 Musello, A.; Garzon, E.; Lanuzza, M.; Procel, L. M.; Taco, R.
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing | 1-gen-2023 | Moposita, T.; Garzon, E.; Crupi, F.; Trojman, L.; Vladimirescu, A.; Lanuzza, M. | |
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator | 1-gen-2008 | Perri, Stefania; Corsonello, Pasquale | |
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers | 1-gen-2022 | Frustaci, Fabio; Spagnolo, Fanny; Perri, Stefania; Corsonello, Pasquale | |
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory | 1-gen-2023 | Garzon, E.; Golman, R.; Lanuzza, M.; Teman, A.; Yavits, L. | |
Low-Power Level Shifter for Multi-Supply Voltage Designs | 1-gen-2012 | Lanuzza, M.; Corsonello, P.; Perri, S. | |
Multi-Bit Full Comparator Logic in Quantum-Dot Cellular Automata | 1-gen-2022 | Perri, S.; Spagnolo, F.; Frustaci, F.; Corsonello, P. | |
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter | 1-gen-2021 | Fassio, L.; Settino, F.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M. | |
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths | 1-gen-2020 | Stanger, I.; Shavit, N.; Taco, R.; Lanuzza, M.; Fish, A. | |
An Ultralow-Voltage Energy-Efficient Level Shifter | 1-gen-2017 | Lanuzza, Marco; Crupi, Felice; Rao, S; DE ROSE, Raffaele; Strangio, S; Iannaccone, G. | |
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements | 1-gen-2012 | Crupi, Felice; Alioto, M; Franco, J; Magnone, P; Togo, M; Horiguchi, N; Groeseneken, G. | |
XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs | 1-gen-2023 | Musello, A.; Garzon, E.; Lanuzza, M.; Procel, L. M.; Taco, R. |
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