Sfoglia per Autore
Simulation of an improved neural based A/D converter
1993-01-01 Cappuccino, Gregorio; Corsonello, P.
Design and demonstration of high throughput square rooting circuit
1996-01-01 Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, Giuseppe
Design and demonstration of a real time processor for one-bit coded SAR signals
1996-01-01 Cappuccino, Gregorio; Cocorullo, Giuseppe; Corsonello, Pasquale; Schirinzi, G.
Real-time processing of one-bit coded SAR data
1996-01-01 Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, G.; Schirinzi, G.
High throughput combined division square root unit
1998-01-01 Corsonello, Pasquale; Cappuccino, Gregorio; Cocorullo, Giuseppe
Estimation of power dissipation for lossy transmission lines in high speed VLSI CMOS circuits
1998-01-01 Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, G.
High performance VLSI modules for division and square root
1998-01-01 Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, Giuseppe
CMOS buffer sizing for long on-chip interconnects
1998-01-01 Cappuccino, Gregorio; Cocorullo, Giuseppe; Corsonello, Pasquale
Educational design of high-performance arithmetic circuits on FPGA
1999-01-01 Cappuccino, Gregorio; Cocorullo, Giuseppe; Corsonello, Pasquale; Perri, S.
Time-domain Model for Power Dissipation of CMOS Buffers Driving Lossy Lines
1999-01-01 Cappuccino, Gregorio; Cocorullo, Giuseppe
A Time-domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines
1999-01-01 Cappuccino, Gregorio; Cocorullo, G.
High speed self-timed pipelined datapath for square rooting
1999-01-01 Cappuccino, Gregorio; Cocurullo, G; Corsonello, Pasquale; Perri, Stefania
Estimation of power dissipation for transmission lines in deep-submicrometer ULSI circuits
1999-01-01 Cappuccino, Gregorio; Cocorullo, G; Corsonello, Pasquale
High speed division and square root modules for asynchronous datapaths
2000-01-01 Cocorullo, Giuseppe; Corsonello, Pasquale; Perri, S; Cappuccino, Gregorio
FDTD Analysis of Power Dissipation in VLSI Lossy Interconnects
2000-01-01 Amendola, G.; Cappuccino, Gregorio; Ramahi, O. M.
Time-domain macromodel for lossy VLSI interconnects
2000-01-01 Cappuccino, Gregorio; Cocorullo, Giuseppe
CMOS Sizing Rule for High Performance Long Interconnects
2001-01-01 Cappuccino, Gregorio; Cocorullo, G.
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing
2001-01-01 Cappuccino, G.; Cocorullo, G.; Corsonello, Pasquale; Perri, Stefania; Staino, G.
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits
2001-01-01 Perri, Stefania; Corsonello, Pasquale; Cocorullo, Giuseppe; Cappuccino, Gregorio; Staino, G.
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines
2001-01-01 Cappuccino, Gregorio; Corsonell, P.; Cocorullo, G.; Perri, S.; Staino, G.
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
Simulation of an improved neural based A/D converter | 1-gen-1993 | Cappuccino, Gregorio; Corsonello, P. | |
Design and demonstration of high throughput square rooting circuit | 1-gen-1996 | Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, Giuseppe | |
Design and demonstration of a real time processor for one-bit coded SAR signals | 1-gen-1996 | Cappuccino, Gregorio; Cocorullo, Giuseppe; Corsonello, Pasquale; Schirinzi, G. | |
Real-time processing of one-bit coded SAR data | 1-gen-1996 | Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, G.; Schirinzi, G. | |
High throughput combined division square root unit | 1-gen-1998 | Corsonello, Pasquale; Cappuccino, Gregorio; Cocorullo, Giuseppe | |
Estimation of power dissipation for lossy transmission lines in high speed VLSI CMOS circuits | 1-gen-1998 | Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, G. | |
High performance VLSI modules for division and square root | 1-gen-1998 | Cappuccino, Gregorio; Corsonello, Pasquale; Cocorullo, Giuseppe | |
CMOS buffer sizing for long on-chip interconnects | 1-gen-1998 | Cappuccino, Gregorio; Cocorullo, Giuseppe; Corsonello, Pasquale | |
Educational design of high-performance arithmetic circuits on FPGA | 1-gen-1999 | Cappuccino, Gregorio; Cocorullo, Giuseppe; Corsonello, Pasquale; Perri, S. | |
Time-domain Model for Power Dissipation of CMOS Buffers Driving Lossy Lines | 1-gen-1999 | Cappuccino, Gregorio; Cocorullo, Giuseppe | |
A Time-domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines | 1-gen-1999 | Cappuccino, Gregorio; Cocorullo, G. | |
High speed self-timed pipelined datapath for square rooting | 1-gen-1999 | Cappuccino, Gregorio; Cocurullo, G; Corsonello, Pasquale; Perri, Stefania | |
Estimation of power dissipation for transmission lines in deep-submicrometer ULSI circuits | 1-gen-1999 | Cappuccino, Gregorio; Cocorullo, G; Corsonello, Pasquale | |
High speed division and square root modules for asynchronous datapaths | 1-gen-2000 | Cocorullo, Giuseppe; Corsonello, Pasquale; Perri, S; Cappuccino, Gregorio | |
FDTD Analysis of Power Dissipation in VLSI Lossy Interconnects | 1-gen-2000 | Amendola, G.; Cappuccino, Gregorio; Ramahi, O. M. | |
Time-domain macromodel for lossy VLSI interconnects | 1-gen-2000 | Cappuccino, Gregorio; Cocorullo, Giuseppe | |
CMOS Sizing Rule for High Performance Long Interconnects | 1-gen-2001 | Cappuccino, Gregorio; Cocorullo, G. | |
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing | 1-gen-2001 | Cappuccino, G.; Cocorullo, G.; Corsonello, Pasquale; Perri, Stefania; Staino, G. | |
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits | 1-gen-2001 | Perri, Stefania; Corsonello, Pasquale; Cocorullo, Giuseppe; Cappuccino, Gregorio; Staino, G. | |
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines | 1-gen-2001 | Cappuccino, Gregorio; Corsonell, P.; Cocorullo, G.; Perri, S.; Staino, G. |
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