IRIS

Sfoglia per Rivista  IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS

Opzioni
Vai a: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Mostrati risultati da 1 a 20 di 21
Titolo Data di pubblicazione Autore(i) File
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1-gen-2022 Zambrano, Benjamin; Garzon, Esteban; Strangio, S.; Crupi, F.; Lanuzza, M.
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 1-gen-2021 Perri, S.; Spagnolo, F.; Frustaci, F.; Corsonello, P.
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 1-gen-2022 Spagnolo, Fanny; Perri, Stefania; Corsonello, Pasquale
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 1-gen-2012 Frustaci, Fabio; Corsonello, Pasquale; Perri, Stefania
Approximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation 1-gen-2020 Frustaci, F.; Perri, S.; Corsonello, P.; Alioto, M.
Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications 1-gen-2021 Amendola, G.; Boccia, L.; Centurelli, F.; Chevalier, P.; Fonte, A.; Mustacchio, C.; Pallotta, A.; Tommasino, P.; Traversa, A.; Trifiletti, A.
Design of Efficient BCD adders in Quantum Dot Cellular Automata 1-gen-2017 Cocorullo, G; Corsonello, Pasquale; Frustaci, F; Perri, Stefania
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers 1-gen-2008 Pugliese, A; Cappuccino, Gregorio; Cocorullo, Giuseppe
Designing High-Speed Adders in Power-Constrained Environments 1-gen-2009 Frustaci, F; Lanuzza, Marco; Zicari, P; Perri, Stefania; Corsonello, Pasquale
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing 1-gen-2023 Moposita, T.; Garzon, E.; Crupi, F.; Trojman, L.; Vladimirescu, A.; Lanuzza, M.
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator 1-gen-2008 Perri, Stefania; Corsonello, Pasquale
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 1-gen-2022 Frustaci, Fabio; Spagnolo, Fanny; Perri, Stefania; Corsonello, Pasquale
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory 1-gen-2023 Garzon, E.; Golman, R.; Lanuzza, M.; Teman, A.; Yavits, L.
Low-Power Level Shifter for Multi-Supply Voltage Designs 1-gen-2012 Lanuzza, M.; Corsonello, P.; Perri, S.
Multi-Bit Full Comparator Logic in Quantum-Dot Cellular Automata 1-gen-2022 Perri, S.; Spagnolo, F.; Frustaci, F.; Corsonello, P.
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 1-gen-2021 Fassio, L.; Settino, F.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths 1-gen-2020 Stanger, I.; Shavit, N.; Taco, R.; Lanuzza, M.; Fish, A.
An Ultralow-Voltage Energy-Efficient Level Shifter 1-gen-2017 Lanuzza, Marco; Crupi, Felice; Rao, S; DE ROSE, Raffaele; Strangio, S; Iannaccone, G.
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements 1-gen-2012 Crupi, Felice; Alioto, M; Franco, J; Magnone, P; Togo, M; Horiguchi, N; Groeseneken, G.
Mostrati risultati da 1 a 20 di 21
Legenda icone

  •  file ad accesso aperto
  •  file disponibili sulla rete interna
  •  file disponibili agli utenti autorizzati
  •  file disponibili solo agli amministratori
  •  file sotto embargo
  •  nessun file disponibile