IRIS

Sfoglia per Autore  

Opzioni
Mostrati risultati da 41 a 60 di 70
Titolo Data di pubblicazione Autore(i) File
Double-precision Dual Mode Logic carry-save multiplier 1-gen-2019 De Rose, Raffaele; Romero, Paul; Lanuzza, Marco
An energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops 1-gen-2019 Lanuzza, M.; De Rose, R.; Crupi, F.; Alioto, M.
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs 1-gen-2019 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Finocchio, G.; Carpentieri, M.; Lanuzza, M.
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 1-gen-2019 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Lanuzza, M.
Device-to-system level simulation framework for STT-DMTJ based cache memory 1-gen-2019 Garzon, E.; De Rose, R.; Crupi, F.; Lanuzza, M.
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 1-gen-2020 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Finocchio, G.; Carpentieri, M.; Lanuzza, M.
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 1-gen-2020 Puliafito, V.; De Rose, R.; Crupi, F.; Chiappini, S.; Finocchio, G.; Lanuzza, M.; Carpentieri, M.
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 1-gen-2020 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
Spin-orbit torque based physical unclonable function 1-gen-2020 Finocchio, G.; Moriyama, T.; De Rose, R.; Siracusano, G.; Lanuzza, M.; Puliafito, V.; Chiappini, S.; Crupi, F.; Zeng, Z.; Ono, T.; Carpentieri, M.
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 1-gen-2021 Fassio, L.; Settino, F.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures 1-gen-2021 Garzon, E.; De Rose, R.; Crupi, F.; Carpentieri, M.; Teman, A.; Lanuzza, M.
Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM 1-gen-2021 Garzon, E.; De Rose, R.; Crupi, F.; Trojman, L.; Teman, A.; Lanuzza, M.
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 1-gen-2021 Vatalaro, M.; De Rose, R.; Lanuzza, M.; Iannaccone, G.; Crupi, F.
STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing 1-gen-2021 De Rose, R.; Zanotti, T.; Puglisi, F. M.; Crupi, F.; Pavan, P.; Lanuzza, M.
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 1-gen-2021 Fassio, L.; Lin, L.; De Rose, R.; Lanuzza, M.; Crupi, F.; Alioto, M.
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 1-gen-2021 Garzon, E.; De Rose, R.; Crupi, F.; Teman, A.; Lanuzza, M.
Field-Free Magnetic Tunnel Junction for Logic Operations Based on Voltage-Controlled Magnetic Anisotropy 1-gen-2021 Cutugno, F.; Garzon, Esteban; De Rose, R.; Finocchio, G.; Lanuzza, M.; Carpentieri, M.
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider 1-gen-2022 Vatalaro, M.; De Rose, R.; Lanuzza, M.; Crupi, F.
Mostrati risultati da 41 a 60 di 70
Legenda icone

  •  file ad accesso aperto
  •  file disponibili sulla rete interna
  •  file disponibili agli utenti autorizzati
  •  file disponibili solo agli amministratori
  •  file sotto embargo
  •  nessun file disponibile