IRIS
SPAGNOLO, Fanny
 Distribuzione geografica
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Continente #
NA - Nord America 666
EU - Europa 245
AS - Asia 64
AF - Africa 19
OC - Oceania 3
Totale 997
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Nazione #
US - Stati Uniti d'America 663
IT - Italia 76
DE - Germania 54
UA - Ucraina 46
CN - Cina 31
AT - Austria 17
SE - Svezia 17
SN - Senegal 12
FI - Finlandia 10
EG - Egitto 7
TR - Turchia 7
TW - Taiwan 7
IN - India 6
RS - Serbia 5
SG - Singapore 5
BE - Belgio 4
GB - Regno Unito 4
HK - Hong Kong 4
AU - Australia 3
FR - Francia 3
ID - Indonesia 3
CA - Canada 2
LU - Lussemburgo 2
PL - Polonia 2
AL - Albania 1
ES - Italia 1
LT - Lituania 1
MK - Macedonia 1
MY - Malesia 1
NL - Olanda 1
PA - Panama 1
Totale 997
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Città #
Chandler 252
Jacksonville 29
Rende 25
Shanghai 25
Lawrence 22
Roxbury 22
Bremen 20
Ogden 18
Dearborn 13
Inglewood 13
Dakar 12
Des Moines 12
Vienna 12
Helsinki 9
Ashburn 8
Cambridge 8
Boardman 5
Florence 5
Naples 5
Wilmington 5
Ann Arbor 4
Belgrade 4
Brussels 4
Frankfurt am Main 4
Garbagnate Milanese 4
Izmir 4
Messina 4
San Mateo 4
Scilla 4
Seattle 4
Siegen 4
Syracuse 4
Taipei 4
Giza 3
Istanbul 3
Klosterneuburg 3
Los Angeles 3
New York 3
Norwalk 3
Rizziconi 3
San Francisco 3
Santa Clara 3
Assiut 2
Bandung 2
Banqiao 2
Beijing 2
Bologna 2
Canberra 2
Canosa di Puglia 2
Catanzaro 2
Central 2
Chiaravalle Centrale 2
Corbeil-Essonnes 2
Hesperange 2
Hyderabad 2
Magliano Alpi 2
Tappahannock 2
Torre de' Passeri 2
Amsterdam 1
Berlin 1
Bhubaneswar 1
Brooklyn 1
Chirala 1
Delhi 1
Esslingen am Neckar 1
Fairfield 1
Hsinchu 1
Jakarta 1
Lappeenranta 1
Leno 1
Leven 1
Maranello 1
Marki 1
Mesquite 1
Monza 1
Muadzam Shah 1
Málaga 1
Nanjing 1
Niš 1
Ottawa 1
Port Said 1
Saint-Laurent 1
Shubra al Khaymah 1
Skopje 1
Spanga 1
Spezzano Albanese 1
Sydney 1
The Colony 1
Tirana 1
Turin 1
Vilnius 1
Warsaw 1
Totale 665
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Nome #
An efficient connected component labeling architecture for embedded systems 61
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 58
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 54
Designing Fast Convolutional Engines for Deep Learning Applications 52
Design of Real-Time FPGA-based Embedded System for Stereo Vision 52
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 48
An efficient hardware-oriented single-pass approach for connected component analysis 43
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 41
A parallel connected component labeling architecture for heterogeneous systems-on-chip 40
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 39
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 39
Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs 38
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 38
An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm Implementation in Wearable Embedded Systems 36
An efficient convolution engine based on the à-trous spatial pyramid pooling 36
Designing Energy-Efficient Approximate Multipliers 35
Efficient approximate adders for fpga-based data-paths 35
Parallel architecture of power-of-two multipliers for FPGAS 30
Design of a real-time face detection architecture for heterogeneous systems-on-chips 30
Efficient deconvolution architecture for heterogeneous systems-on-chip 30
Multi-Bit Full Comparator Logic in Quantum-Dot Cellular Automata 26
Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions 25
Run-time adaptive hardware accelerator for convolutional neural networks 23
Stereo vision architecture for heterogeneous systems-on-chip 21
Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree Hardware Accelerators 20
Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip 20
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes 15
Design of Leading Zero Counters on FPGAs 15
Compressed Sensing Approach for Physiological Signals: A Review 12
Design of Approximate Bilateral Filters for Image Denoising on FPGAs 8
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 8
HW/SW Codesign for Approximation-Aware Binary Neural Networks 7
Approximate Foveated-Based Super Resolution Method for Headset Displays 7
Welding defects classification through a Convolutional Neural Network 7
ERMES: Efficient Racetrack Memory Emulation System based on FPGA 6
Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video Processing on FPGA 5
Heterogeneous FPGA-based System for Real-Time Drowsiness Detection 3
Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-based HW Accelerators 3
Totale 1.066
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Categoria #
all - tutte 8.835
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 8.835
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20196 0 0 0 0 0 0 0 0 0 0 5 1
2019/202053 5 5 0 4 2 15 2 4 6 1 8 1
2020/202183 10 0 9 8 0 7 1 17 10 16 0 5
2021/2022142 0 6 0 9 15 0 3 12 3 0 29 65
2022/2023518 26 44 9 72 60 65 1 64 74 25 47 31
2023/2024255 45 19 50 22 18 18 6 27 31 18 1 0
Totale 1.066