IRIS
TACO LASSO, Edison Ramiro
 Distribuzione geografica
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Continente #
NA - Nord America 568
EU - Europa 311
AS - Asia 238
AF - Africa 11
SA - Sud America 1
Totale 1.129
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Nazione #
US - Stati Uniti d'America 553
SG - Singapore 147
UA - Ucraina 111
DE - Germania 73
CN - Cina 49
IT - Italia 30
FI - Finlandia 25
SE - Svezia 23
NL - Olanda 16
CA - Canada 15
IQ - Iraq 13
TR - Turchia 13
HK - Hong Kong 11
SN - Senegal 10
BE - Belgio 9
GB - Regno Unito 6
AT - Austria 5
FR - Francia 3
LV - Lettonia 2
RO - Romania 2
BR - Brasile 1
GE - Georgia 1
HR - Croazia 1
IE - Irlanda 1
IN - India 1
JP - Giappone 1
KR - Corea 1
MD - Moldavia 1
NO - Norvegia 1
PH - Filippine 1
PT - Portogallo 1
RU - Federazione Russa 1
SL - Sierra Leone 1
Totale 1.129
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Città #
Singapore 118
Chandler 93
Boardman 59
Jacksonville 56
San Mateo 35
Dearborn 34
Helsinki 24
Lawrence 22
Roxbury 22
Shanghai 19
Des Moines 18
Amsterdam 15
Cambridge 15
Ashburn 14
Bremen 14
Milan 13
Izmir 11
Ogden 11
Dakar 10
Brussels 9
Ottawa 8
Rende 8
Ann Arbor 7
Toronto 6
West Jordan 6
Beijing 5
Chicago 5
Hong Kong 5
Los Angeles 5
Falkenstein 4
Monmouth Junction 4
New York 4
Vienna 4
Brooklyn 3
Inglewood 3
London 3
San Francisco 3
Seattle 3
Wilmington 3
Bari 2
Catanzaro 2
Cedar Knolls 2
Corsico 2
Guangzhou 2
Houston 2
Jiaxing 2
Norwalk 2
Riga 2
Timișoara 2
Yiwu 2
Andover 1
Augusta 1
Baoding 1
Chisinau 1
Dublin 1
Ergolding 1
Forest City 1
Freetown 1
Grafing 1
Istanbul 1
Kilburn 1
Lappeenranta 1
Lessolo 1
Lisbon 1
Marseille 1
Montreal 1
Nanjing 1
Ningbo 1
Oslo 1
Palermo 1
Redmond 1
Redwood City 1
Santa Clara 1
Shenzhen 1
Streamwood 1
Tbilisi 1
Tiantai Chengguanzhen 1
Tokyo 1
Washington 1
Xi'an 1
Zagreb 1
Zamboanga City 1
Totale 755
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Nome #
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET 122
A 180 nm Low-Cost Operational Amplifier for IoT Applications 67
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI 63
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 61
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 60
Evaluation of Dual Mode Logic in 28nm FD-SOI technology 59
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI 55
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design 46
Live demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI 46
Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology 44
Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI 43
Dynamic gate-level body biasing for subthreshold digital design 43
Ultra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits 41
Improving speed and power characteristics of pulse-triggered flip-flops 37
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths 29
Energy efficient self-adaptive dual mode logic address decoder 27
Ultralow voltage finFET-versus TFET-based STT-MRAM cells for iot applications 27
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator 22
Live demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET 21
Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications 20
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories 19
Live Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths 19
Exploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology 19
Exploiting TFET-based technology for energy-efficient STT-MRAM cells 18
Robust dual mode pass logic (DMPL) for energy efficiency and high performance 17
Design of an Air Pollution Monitoring System Based on a Low-Cost Sensor Node 16
RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies 14
Designing Precharge-Free Energy-Efficient Content-Addressable Memories 11
FlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic 10
Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective 9
XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs 9
IoT sensor nodes for air pollution monitoring: a review 8
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic 7
Efficiency of Dual Mode Logic in Nanoscale Technology Nodes 7
720p-HD Gray-scale and Color Images Shape Recognition System Implementation on an FPGA Platform with a 1080pFull-HD HDMI Interface using a Hu Moments Algorithm 6
Dual mode logic address decoder 6
Assessment of a universal logic gate and a full adder circuit based on CMOS-memristor technology 6
Effects of the technology scaling down to 28nm on Ultra-Low Voltage and Power OTA performance using TCAD simulations 6
DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems 6
Method for mitigation of droop timing errors including a droop detector and dual mode logic 5
Valorization of ripe banana peels and cocoa pod husk hydrochars as green sustainable “low loss” dielectric materials 5
Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells 5
From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits 5
Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits 5
Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow 4
Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages 4
Process variation-aware datapath employing dual mode logic 4
Process variation-aware datapath employing dual mode logic 3
Voltage-Divider-Based Binary and Ternary Content-Addressable Memory (CAM) Exploiting Double-Barrier Magnetic Tunnel Junction 3
Implementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node 3
IEEE CASS Tour Ecuador 2023 3
Totale 1.195
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Categoria #
all - tutte 11.609
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 11.609
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/202041 0 0 0 0 0 0 3 14 3 1 12 8
2020/202188 12 0 12 12 4 10 0 17 0 12 1 8
2021/2022234 11 47 0 17 7 2 6 36 4 3 31 70
2022/2023242 31 33 9 20 46 17 2 21 31 10 11 11
2023/2024161 18 8 14 6 7 7 3 13 18 21 10 36
2024/2025305 7 66 17 50 83 80 2 0 0 0 0 0
Totale 1.195