IRIS
CAPPUCCINO, Gregorio
 Distribuzione geografica
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Continente #
NA - Nord America 2.449
AS - Asia 2.365
EU - Europa 1.562
SA - Sud America 730
AF - Africa 172
OC - Oceania 6
Continente sconosciuto - Info sul continente non disponibili 2
AN - Antartide 1
Totale 7.287
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Nazione #
US - Stati Uniti d'America 2.335
SG - Singapore 981
BR - Brasile 560
UA - Ucraina 543
CN - Cina 460
DE - Germania 360
VN - Vietnam 343
HK - Hong Kong 214
IT - Italia 209
FI - Finlandia 142
SE - Svezia 130
SN - Senegal 116
TR - Turchia 93
KR - Corea 75
AR - Argentina 60
CA - Canada 60
FR - Francia 48
IN - India 42
MX - Messico 38
BD - Bangladesh 31
GB - Regno Unito 31
EC - Ecuador 29
RU - Federazione Russa 27
ID - Indonesia 22
BE - Belgio 21
CO - Colombia 20
IQ - Iraq 18
PK - Pakistan 16
ZA - Sudafrica 16
PY - Paraguay 15
VE - Venezuela 15
PL - Polonia 13
CL - Cile 12
UY - Uruguay 10
UZ - Uzbekistan 10
EG - Egitto 9
MA - Marocco 9
PE - Perù 9
KE - Kenya 8
JP - Giappone 7
NL - Olanda 7
AU - Australia 6
IR - Iran 6
IE - Irlanda 5
TN - Tunisia 5
CR - Costa Rica 4
DZ - Algeria 4
ES - Italia 4
JM - Giamaica 4
JO - Giordania 4
KZ - Kazakistan 4
RO - Romania 4
AE - Emirati Arabi Uniti 3
AT - Austria 3
AZ - Azerbaigian 3
BY - Bielorussia 3
KG - Kirghizistan 3
LB - Libano 3
MY - Malesia 3
NP - Nepal 3
SA - Arabia Saudita 3
TT - Trinidad e Tobago 3
AM - Armenia 2
BH - Bahrain 2
CZ - Repubblica Ceca 2
DO - Repubblica Dominicana 2
GE - Georgia 2
LA - Repubblica Popolare Democratica del Laos 2
NG - Nigeria 2
PS - Palestinian Territory 2
SK - Slovacchia (Repubblica Slovacca) 2
AO - Angola 1
AQ - Antartide 1
BA - Bosnia-Erzegovina 1
BN - Brunei Darussalam 1
CG - Congo 1
CH - Svizzera 1
DK - Danimarca 1
EE - Estonia 1
EU - Europa 1
GA - Gabon 1
GR - Grecia 1
GT - Guatemala 1
HU - Ungheria 1
KH - Cambogia 1
KW - Kuwait 1
MD - Moldavia 1
MN - Mongolia 1
OM - Oman 1
PA - Panama 1
QA - Qatar 1
RS - Serbia 1
SV - El Salvador 1
TH - Thailandia 1
TW - Taiwan 1
XK - ???statistics.table.value.countryCode.XK??? 1
Totale 7.287
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Città #
Jacksonville 399
Singapore 398
Chandler 330
Hong Kong 212
Dearborn 205
Boardman 184
Helsinki 141
Ho Chi Minh City 127
Beijing 126
Dallas 117
Dakar 115
San Mateo 104
Lawrence 85
Roxbury 85
Izmir 79
Seoul 75
Ashburn 72
Hanoi 72
Hefei 66
Shanghai 66
Ann Arbor 64
Falkenstein 55
Des Moines 54
Cambridge 52
Ottawa 37
São Paulo 34
Wilmington 30
Ogden 29
Milan 28
Inglewood 26
Rende 26
Brussels 21
Grafing 20
Council Bluffs 18
Haiphong 18
Los Angeles 17
New York 16
Seattle 16
Cosenza 14
San Francisco 14
Frankfurt am Main 13
Pune 13
Rio de Janeiro 13
Thái Bình 13
Brooklyn 12
Curitiba 12
Munich 12
Guayaquil 11
Mexico City 11
The Dalles 11
Tianjin 11
Guarulhos 10
Asunción 9
Chicago 9
Columbus 9
Guangzhou 9
Hải Dương 9
Salvador 9
Brasília 8
Dhaka 8
Houston 8
Pisa 8
Quito 8
Ribeirão Preto 8
Boston 7
Jiaxing 7
Lamezia Terme 7
Lima 7
Manaus 7
Montreal 7
Nairobi 7
Santa Clara 7
Tashkent 7
Toronto 7
Warsaw 7
Amsterdam 6
Atlanta 6
Bogotá 6
Campinas 6
Can Tho 6
Chennai 6
Juiz de Fora 6
Montevideo 6
Nanjing 6
Reggio Calabria 6
Shenzhen 6
Tokyo 6
Windsor 6
Wroclaw 6
Wuhan 6
Araçatuba 5
Baghdad 5
Bauru 5
Belo Horizonte 5
Bexley 5
Biên Hòa 5
Bắc Giang 5
Cairo 5
Caracas 5
Chiusa di Pesio 5
Totale 4.108
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Nome #
Advanced Lead-Acid battery management for low-TCO stationary storage systems 135
Design and demonstration of a real time processor for one-bit coded SAR signals 128
Adaptive Charging of Lead Acid batteries for Maximum Efficiency and Cycle Lifetime 127
High speed division and square root modules for asynchronous datapaths 116
A new efficient SC integrator scheme for high-speed low power applications 112
Design approach for fast-settling two-stage amplifiers employing current-buffer Miller compensation 111
CMOS buffer sizing for long on-chip interconnects 110
Design approach for high-bandwidth low-power three-stage operational amplifiers 106
High speed self-timed pipelined datapath for square rooting 106
A Review of Non-Destructive Techniques for Lithium-Ion Battery Performance Analysis 101
Design and demonstration of high throughput square rooting circuit 101
Time-domain Model for Power Dissipation of CMOS Buffers Driving Lossy Lines 100
Optimal Traction Battery Module Sizing for Cost-effective Second Life Reuse 100
Advantages of efficiency-aware smart charging strategies for PEVs 98
Corrections to Settling Time Optimization for Three-Stage CMOS Amplifier Topologies (vol 56, pg 2569, 2009) 97
Channel Widening Effect on the Effective Output Resistance of Deep-Submicron CMOS Line Driver and its Application to Repeater Insertion 97
High performance VLSI modules for division and square root 96
Impact of the variable output resistance on the transient response of LC transmission line CMOS buffers and its model 95
Buffer output capacitance effect on NoC line drivers performance 95
Sistema e metodo per la gestione della carica e scarica di accumulatori 95
High throughput combined division square root unit 94
Nested Miller compensation capacitor sizing rules for fast-settling amplifier design 94
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications 94
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 94
Simulation and timing performances of integrated waveguides for ultra-high speed interconnects 93
Circuito di retroazione a capacità commutate per amplificatori operazionali e metodo per pilotare la rete di retroazione 93
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique 92
Analysis of op-amp phase margin impact on SC Sigma Delta modulator performance 92
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances 91
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 91
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines 90
metodo per la caratterizzazione di accumulatori 90
Method for the characterisation of accumulators 90
Performance of current mirror with high-k gate dielectrics 89
Estimation of power dissipation for transmission lines in deep-submicrometer ULSI circuits 88
A Time-domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines 88
Educational design of high-performance arithmetic circuits on FPGA 85
Efficient Architecture for High-Speed Low-Power SC ΣΔ Modulators 84
CMOS Sizing Rule for High Performance Long Interconnects 84
Real-time processing of one-bit coded SAR data 83
Effective Models for Electronic Devices Interconnect: a final user perspective 82
Design of a 75 nW, 0.5 V Subthreshold CMOS Operational Amplifier 82
Electric Vehicles, Smart Charging and Smart Grids 81
Integrated Waveguides for Ultra-High Speed Interconnects 81
sistema e metodo per la misura e la predizione dell'efficienza di carica di accumulatori 81
Class-AB Output Stage Design for High-Speed Three-Stage Op-Amps 81
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects 80
Improved efficiency management strategy for battery-based energy storage systems 80
Simulation of PCB Structures for Ultra Gigabit Communication 79
Settling Time Optimisation for Two-Stage CMOS Amplifiers With Current-Buffer Miller Compensation - errata 78
Metodologia per la progettazione della rete di compensazione di un amplificatore innestato di Miller tramite contorno delle radici 78
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers 77
SYSTEM AND METHOD FOR THE MEASUREMENT AND PREDICTION OF THE CHARGING EFFICIENCY OF ACCUMULATORS 76
Estimation of power dissipation for lossy transmission lines in high speed VLSI CMOS circuits 75
Large-Signal Settling Optimization of SC Circuits Using Two-Stage Amplifiers with Current-Buffer Miller Compensation 75
Potentiality of Variable-rate PEVs Charging Strategies for Smart Grids 74
Settling Time Minimization of Operational Amplifiers 74
Efficient switched-capacitor common-mode feedback circuit for high-speed low-power amplifiers 73
METHOD FOR CHARACTERIZATION OF ACCUMULATORS AND RELATED 73
Slewing investigation and improved design rules for SC circuits employing two-stage amplifiers with current-buffer Miller compensation Istanbul, 2008, 2008, pp. - 72
Operating Mode Analysis of Deep-Submicron CMOS Buffers Driving Inductive Interconnects 72
Fiber Bragg grating sensors based system for strain measurements 70
sistema e metodo di energy harvesting da vibrazioni meccaniche e radiazioni elettromagnetiche 70
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation 70
Settling Time Optimisation for Two-Stage CMOS Amplifiers With Current-Buffer Miller Compensation 69
Impact of charging efficiency variations on the effectiveness of variable-rate-based charging strategies for electric vehicles 68
Design Considerations for Fast-Settling Two-Stage Miller-Compensated Operational Amplifiers 68
SETTLING-TIME-ORIENTED DESIGN PROCEDURE FOR TWO-STAGE AMPLIFIERS WITH CURRENT-BUFFER MILLER COMPENSATION 68
Time-domain macromodel for lossy VLSI interconnects 66
Simulation of an improved neural based A/D converter 66
Design Methodology of Nested Miller Amplifiers for Small Capacitive Loads 66
FDTD Analysis of Power Dissipation in VLSI Lossy Interconnects 66
Effect of Op-Amp Phase Margin on SC Sigma-Delta Modulator Performances 66
sistema per lo scambio intelligente di energia elettrica tra la rete di distribuzione elettrica ed una batteria 66
Spent Lithium Battery Recycling: Traditional and Innovative Approaches 65
Progettazione e Realizzazione di un Sistema Cambio Elettroattuato per Kart da Competizione 65
Output Capacitance Effect on CMOS Line Repeaters 65
RecyBat24: a dataset for detecting lithium-ion batteries in electronic waste disposal 64
Design criterion for high-speed low-power SC circuits 64
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers 61
IEEE Real World Engineering Projects: Discovery-Based Curriculum Modules for First-Year Students 61
Impact of Channel-Length Modulation on the Transient Response of CMOS Gates Driving LC-Lines 61
Settling-time-oriented design procedure for two-stage amplifiers with current-buffer Miller compensation 59
Enhancement in Lithium Recovery from Spent Lithium Batteries by Nanofiltration Membranes 57
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Line 57
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies 56
Effect of the integrator settling behavior on SC ΣΔ modulator characteristics: A theoretical study 55
OPTIMAL SHUNT INDUCTANCE SIZING FOR HIGH PULSE FIDELITY WIDEBAND AMPLIFIERS 52
Efficiency-oriented smart energy management strategies for domestic energy storage systems integrated with EVs charging 52
Totale 7.322
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Categoria #
all - tutte 46.995
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 46.995
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021354 0 0 0 0 0 89 6 85 3 89 5 77
2021/2022708 9 38 18 40 74 27 5 139 5 16 103 234
2022/2023739 110 51 16 96 71 71 2 166 97 17 13 29
2023/2024346 39 10 18 4 17 44 8 33 50 13 15 95
2024/20251.405 81 185 43 39 80 229 47 54 134 50 114 349
2025/20262.450 501 170 392 526 750 111 0 0 0 0 0 0
Totale 7.322