IRIS
FRUSTACI, Fabio
 Distribuzione geografica
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Continente #
NA - Nord America 2.036
EU - Europa 1.071
AS - Asia 532
AF - Africa 96
SA - Sud America 19
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 2
Totale 3.758
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Nazione #
US - Stati Uniti d'America 2.006
UA - Ucraina 392
SG - Singapore 256
DE - Germania 248
IT - Italia 178
CN - Cina 173
SE - Svezia 110
SN - Senegal 88
TR - Turchia 58
FI - Finlandia 52
CA - Canada 29
BE - Belgio 21
BR - Brasile 16
IN - India 15
AT - Austria 13
GB - Regno Unito 12
FR - Francia 9
HK - Hong Kong 8
TW - Taiwan 8
RS - Serbia 7
NL - Olanda 5
RU - Federazione Russa 5
EG - Egitto 4
ID - Indonesia 4
KR - Corea 4
ES - Italia 3
AL - Albania 2
AU - Australia 2
CH - Svizzera 2
EU - Europa 2
GR - Grecia 2
LU - Lussemburgo 2
MA - Marocco 2
PL - Polonia 2
AR - Argentina 1
BD - Bangladesh 1
BG - Bulgaria 1
CL - Cile 1
CZ - Repubblica Ceca 1
IL - Israele 1
JP - Giappone 1
LT - Lituania 1
LV - Lettonia 1
MK - Macedonia 1
MY - Malesia 1
PA - Panama 1
PE - Perù 1
PK - Pakistan 1
SI - Slovenia 1
TH - Thailandia 1
TN - Tunisia 1
ZW - Zimbabwe 1
Totale 3.758
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Città #
Chandler 450
Jacksonville 256
Singapore 196
Boardman 174
Dearborn 129
San Mateo 97
Dakar 88
Rende 83
Lawrence 64
Roxbury 64
Shanghai 55
Helsinki 50
Izmir 50
Ann Arbor 47
Bremen 43
Des Moines 43
Inglewood 32
Ogden 32
Cambridge 31
Ottawa 24
Ashburn 22
Beijing 21
Brussels 21
Brooklyn 15
Vienna 13
Wilmington 13
Los Angeles 10
New York 9
San Francisco 8
Santa Clara 8
Guangzhou 7
Bari 6
Rome 6
Florence 5
Istanbul 5
Naples 5
Norwalk 5
Seattle 5
Amsterdam 4
Belgrade 4
Falkenstein 4
Falls Church 4
Frankfurt am Main 4
Garbagnate Milanese 4
Shenzhen 4
Syracuse 4
Taipei 4
Toronto 4
Berlin 3
Brescia 3
Central 3
Cerzeto 3
Chennai 3
Edinburgh 3
Giza 3
Grafing 3
Hefei 3
Hyderabad 3
Jiaxing 3
Jinan 3
Mascalucia 3
Messina 3
Nanjing 3
Rizziconi 3
Seoul 3
São Paulo 3
Visakhapatnam 3
Bandung 2
Banqiao 2
Bologna 2
Bristol 2
Canosa di Puglia 2
Castrolibero 2
Chiaravalle Centrale 2
Columbus 2
Comiso 2
Hangzhou 2
Hesperange 2
Lappeenranta 2
Lausanne 2
Le Pré-saint-gervais 2
Leipzig 2
London 2
Munich 2
Ningbo 2
Quanzhou 2
Thessaloniki 2
Tirana 2
Torre de' Passeri 2
Tradate 2
Turin 2
Verona 2
Warsaw 2
Zhengzhou 2
Atibaia 1
Bangkok 1
Bauru 1
Bhubaneswar 1
Brasília 1
Capua 1
Totale 2.349
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Nome #
Designing Dynamic Carry Skip Adders: Analysis and Comparison 89
SRAM for error-tolerant applications with dynamic energy-quality management in 28 nm CMOS 78
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 77
Multimodal background subtraction for high-performance embedded systems 73
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 73
Low-power split-path data-driven dynamic logic 72
Comparative analysis of yield optimized pulsed flip-flops 72
An efficient connected component labeling architecture for embedded systems 72
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 72
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 71
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 71
Approximate SRAMs with Dynamic Energy-Quality Management 71
A novel background subtraction method based on color invariants and grayscale levels 68
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 67
A low-leakage single ended 6T SRAM cell 66
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 66
Techniques for leakage energy reduction in deep submicrometer cache memories 64
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 64
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 63
A new noise-tolerant dynamic logic circuit design 62
Design and evaluation of high-speed energy-aware carry skip adders 60
Designing Fast Convolutional Engines for Deep Learning Applications 60
Design of Efficient BCD adders in Quantum Dot Cellular Automata 59
A New optimized high-speed low-power Data-Driven Dynamic (D3L) 32-bit Kogge-Stone adder 59
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse 59
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 59
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 59
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 58
Design of Real-Time FPGA-based Embedded System for Stereo Vision 58
Design of efficient QCA multiplexers 57
An Efficient Hardware-Oriented Stereo Matching Algorithm 55
Accurate power estimation model for CMOS adders optimization 55
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS 55
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 55
An embedded machine vision system for an in-line quality check of assembly processes 55
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 54
A new low-power high-speed single-clock-cycle binary comparator 54
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 54
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 52
Designing High-Speed Adders in Power-Constrained Environments 52
Color Invariant Study for Background Subtraction 50
Approximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation 49
Multimodal background subtraction for high-performance embedded systems 49
An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm Implementation in Wearable Embedded Systems 47
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 47
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 47
Embedded surveillance system using background subtraction and Raspberry Pi 45
Efficient approximate adders for fpga-based data-paths 45
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 45
Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis 43
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 43
Stereo vision architecture for heterogeneous systems-on-chip 43
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 42
Designing Energy-Efficient Approximate Multipliers 39
Energy-efficient single-clock-cycle binary comparator 39
A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS 38
Parallel architecture of power-of-two multipliers for FPGAS 38
Power supply noise in accurate delay model for the sub-threshold domain 38
An explainable embedded neural system for on-board ship detection from optical satellite imagery 37
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology 34
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology 34
Impact of oxide thickness on performances of logic circuits: a predictive simulation study 33
Design and analysis of a leading one detector-based approximate multiplier on FPGA 32
Multi-Bit Full Comparator Logic in Quantum-Dot Cellular Automata 31
Leakage Energy Reduction Techniques in Deep Submicron Cache Memories: A Comparative Study 31
VLSI design of low-leakage single-ended 6T SRAM cell 31
Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree Hardware Accelerators 30
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization 29
Optimization and Evaluation of Tapered-VTH Approach for Energy-Efficient CMOS Buffers 27
Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip 26
Design of Approximate Bilateral Filters for Image Denoising on FPGAs 23
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes 22
Design of Leading Zero Counters on FPGAs 22
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 20
Welding defects classification through a Convolutional Neural Network 19
HW/SW Codesign for Approximation-Aware Binary Neural Networks 14
Approximate Foveated-Based Super Resolution Method for Headset Displays 14
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations 12
Improving the quality degradation of dynamically configurable approximate multipliers via data correlation 11
Efficient implementation of signed multipliers on FPGAs 9
Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs 9
Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-based HW Accelerators 9
Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors 6
Totale 3.892
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Categoria #
all - tutte 31.049
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 31.049
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020335 0 0 0 0 0 141 34 58 12 12 57 21
2020/2021441 64 1 52 59 3 50 5 70 24 61 7 45
2021/2022648 5 78 1 42 72 8 8 114 7 4 114 195
2022/2023991 92 93 15 120 124 119 5 157 121 38 60 47
2023/2024543 76 23 61 27 29 29 13 30 50 20 70 115
2024/2025556 44 224 20 70 118 80 0 0 0 0 0 0
Totale 3.892