IRIS
DE ROSE, Raffaele
 Distribuzione geografica
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Continente #
NA - Nord America 1.777
EU - Europa 982
AS - Asia 161
AF - Africa 70
OC - Oceania 4
SA - Sud America 2
Continente sconosciuto - Info sul continente non disponibili 1
Totale 2.997
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Nazione #
US - Stati Uniti d'America 1.733
UA - Ucraina 336
DE - Germania 222
IT - Italia 147
SE - Svezia 144
CN - Cina 74
SN - Senegal 69
CA - Canada 43
FI - Finlandia 36
TR - Turchia 30
HK - Hong Kong 28
AT - Austria 23
BE - Belgio 23
GB - Regno Unito 18
FR - Francia 12
SG - Singapore 12
CZ - Repubblica Ceca 8
IN - India 6
AU - Australia 4
KR - Corea 4
NL - Olanda 3
IE - Irlanda 2
PL - Polonia 2
AE - Emirati Arabi Uniti 1
BR - Brasile 1
EU - Europa 1
GR - Grecia 1
ID - Indonesia 1
JP - Giappone 1
KW - Kuwait 1
LU - Lussemburgo 1
MO - Macao, regione amministrativa speciale della Cina 1
MX - Messico 1
NO - Norvegia 1
PE - Perù 1
PK - Pakistan 1
RO - Romania 1
RU - Federazione Russa 1
SK - Slovacchia (Repubblica Slovacca) 1
VN - Vietnam 1
ZA - Sudafrica 1
Totale 2.997
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Città #
Chandler 419
Jacksonville 174
San Mateo 166
Dearborn 76
Dakar 69
Lawrence 62
Roxbury 61
Rende 57
New York 48
Bremen 45
Ashburn 40
Des Moines 39
Shanghai 37
Ann Arbor 36
Helsinki 36
Ottawa 34
Brooklyn 32
Wilmington 29
Inglewood 27
Izmir 27
Cambridge 26
Ogden 24
Vienna 21
Brussels 20
Chicago 16
Bari 14
Beijing 14
Munich 14
Cosenza 12
West Jordan 12
Falls Church 11
Redwood City 11
Central 9
London 9
Milan 8
Toronto 8
Boardman 7
Brno 7
Singapore 7
Hong Kong 6
Houston 6
San Francisco 6
Vibo Valentia 6
Frankfurt am Main 5
Kilburn 5
Norwalk 5
Paris 5
Bologna 4
Cedar Knolls 4
Rome 4
Seoul 4
Amsterdam 3
Gunzenhausen 3
Heusden-Zolder 3
Seattle 3
Xi'an 3
Bomporto 2
Brunoy 2
Canberra 2
Catania 2
Changsha 2
Dublin 2
Florence 2
Gravina di Catania 2
Haikou 2
Hefei 2
Jinan 2
Kunming 2
Los Angeles 2
Mascalucia 2
Melbourne 2
Messina 2
Nanjing 2
Ningbo 2
Princeton 2
Turin 2
Athens 1
Augusta 1
Billingstad 1
Bratislava 1
Bursa 1
Bytom 1
Castrovillari 1
Cleveland 1
Danville 1
Esslingen am Neckar 1
Fagnano Castello 1
Falkenstein 1
Fort Lauderdale 1
Gauteng 1
Ho Chi Minh City 1
Hyderabad 1
Islamabad 1
Jakarta 1
Jiaxing 1
Karlsruhe 1
Kuwait City 1
Lima 1
Lincoln 1
Lugugnana 1
Totale 1.903
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Nome #
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 125
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 99
An Ultralow-Voltage Energy-Efficient Level Shifter 87
A Methodology to Account for the Finger Interruptions in Solar Cell Performance 79
A Framework for Energy-Efficiency in Smart Home Environments 79
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 75
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 73
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 70
A comparative study of MWT architectures by means of numerical simulations 67
Comparative analysis of yield optimized pulsed flip-flops 64
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 63
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 63
Design of a sub-1-V nanopower CMOS current reference 63
Collaborative Smart Environments for energy-efficiency and quality of life 62
A methodology to account for the finger non-uniformity in photovoltaic solar cell 61
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 61
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 59
A portable class of 3-transistor current references with low-power sub-0.5 V operation 59
Low energy/delay overhead level shifter for wide-range voltage conversion 58
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 58
Design of a 3T current reference for low-voltage, low-power operation 54
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 54
Design and evaluation of high-speed energy-aware carry skip adders 53
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 53
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 52
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 52
Impact of the Emitter Contact Pattern in c-Si BC-BJ Solar Cells by Numerical Simulations 52
Designing Dynamic Carry Skip Adders: Analysis and Comparison 51
Optimization of Rear Point Contact Geometry by Means of 3-D Numerical Simulation 50
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 49
Numerical Simulation and Modeling of Resistive and Recombination Losses in MWT Solar Cells 48
Spin-orbit torque based physical unclonable function 48
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs 47
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 47
Double-precision Dual Mode Logic carry-save multiplier 46
Device-to-system level simulation framework for STT-DMTJ based cache memory 45
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 45
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 42
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 42
2-D numerical analysis of the impact of the highly-doped profile on selective emitter solar cell performance 42
Two- and three-dimensional numerical simulation of advanced silicon solar cells 42
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 41
Effect of shunt resistance on the performance of mc-Silicon solar cells: A combined electro-optical and thermal investigation 40
Hardware implementation of a Test Lab for Smart Home environments 38
Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis 38
Numerical simulation and modeling of rear point contact solar cells 37
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 37
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 36
Loss analysis of silicon solar cells by means of numerical device simulation 36
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 36
Numerical simulation on the influence of via and rear emitters in MWT solar cells 35
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 35
Understanding the impact of double screen-printing on silicon solar cells by 2-D numerical simulations 33
An energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops 32
Open issues for the numerical simulation of silicon solar cells 28
Design of Ultra-Low Voltage/Power Circuits and Systems 28
Understanding the impact of the doping profiles on selective emitter solar cell by two-dimensional numerical simulation 25
Performance analysis of rear point contact solar cells by three-dimensional numerical simulation 23
Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM 22
Assessment of paper-based MoS2 FET for Physically Unclonable Functions 20
Field-Free Magnetic Tunnel Junction for Logic Operations Based on Voltage-Controlled Magnetic Anisotropy 19
Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures 18
Voltage-controlled magnetic anisotropy based physical unclonable function 15
STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing 15
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V 9
Experimental analysis of variability in WS2-based devices for hardware security 7
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing 3
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing 3
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider 3
Totale 3.151
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Categoria #
all - tutte 22.676
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 22.676
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/201927 0 0 0 0 0 0 0 0 0 0 27 0
2019/2020349 30 29 1 31 22 75 28 33 8 26 46 20
2020/2021367 64 3 45 48 9 38 11 63 8 47 8 23
2021/2022855 20 108 3 45 102 14 10 189 11 27 117 209
2022/2023945 146 91 25 114 150 78 1 120 112 26 35 47
2023/2024466 65 37 37 21 45 74 51 51 52 30 3 0
Totale 3.151