IRIS
DE ROSE, Raffaele
 Distribuzione geografica
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Continente #
NA - Nord America 1.951
EU - Europa 1.050
AS - Asia 437
AF - Africa 70
SA - Sud America 8
OC - Oceania 4
Continente sconosciuto - Info sul continente non disponibili 1
Totale 3.521
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Nazione #
US - Stati Uniti d'America 1.906
UA - Ucraina 336
DE - Germania 235
SG - Singapore 203
IT - Italia 177
CN - Cina 150
SE - Svezia 144
SN - Senegal 69
CA - Canada 44
FI - Finlandia 39
TR - Turchia 32
HK - Hong Kong 28
AT - Austria 24
BE - Belgio 23
GB - Regno Unito 18
CZ - Repubblica Ceca 14
FR - Francia 13
NL - Olanda 12
BR - Brasile 7
IN - India 6
AU - Australia 4
KR - Corea 4
RU - Federazione Russa 3
TW - Taiwan 3
GR - Grecia 2
ID - Indonesia 2
IE - Irlanda 2
MY - Malesia 2
PL - Polonia 2
VN - Vietnam 2
AE - Emirati Arabi Uniti 1
EU - Europa 1
JP - Giappone 1
KW - Kuwait 1
LT - Lituania 1
LU - Lussemburgo 1
MO - Macao, regione amministrativa speciale della Cina 1
MX - Messico 1
NO - Norvegia 1
PE - Perù 1
PK - Pakistan 1
PT - Portogallo 1
RO - Romania 1
SK - Slovacchia (Repubblica Slovacca) 1
ZA - Sudafrica 1
Totale 3.521
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Città #
Chandler 419
Jacksonville 174
San Mateo 166
Boardman 147
Singapore 144
Dearborn 76
Dakar 69
Rende 64
Lawrence 62
Roxbury 61
Shanghai 61
New York 48
Bremen 45
Ashburn 42
Des Moines 39
Helsinki 37
Ann Arbor 36
Ottawa 35
Brooklyn 32
Wilmington 29
Inglewood 27
Izmir 27
Cambridge 26
Munich 24
Ogden 24
Vienna 21
Brussels 20
Chicago 16
Beijing 15
Bari 14
Brno 12
Cosenza 12
Milan 12
West Jordan 12
Falls Church 11
Redwood City 11
Amsterdam 10
Central 9
London 9
Guangzhou 8
Toronto 8
Santa Clara 7
Hong Kong 6
Houston 6
Los Angeles 6
Paris 6
Rome 6
San Francisco 6
Turin 6
Vibo Valentia 6
Frankfurt am Main 5
Kilburn 5
Norwalk 5
Bologna 4
Cedar Knolls 4
Seoul 4
Gunzenhausen 3
Heusden-Zolder 3
Seattle 3
Xi'an 3
Athens 2
Bomporto 2
Brunoy 2
Canberra 2
Carrara 2
Catania 2
Changsha 2
Dublin 2
Florence 2
Gravina di Catania 2
Haikou 2
Hefei 2
Ho Chi Minh City 2
Istanbul 2
Jiaxing 2
Jinan 2
Kunming 2
Lappeenranta 2
Mascalucia 2
Melbourne 2
Messina 2
Nanjing 2
Ningbo 2
Princeton 2
Atibaia 1
Augusta 1
Billingstad 1
Bratislava 1
Brusque 1
Bursa 1
Bytom 1
Castrovillari 1
Caxias do Sul 1
Chongqing 1
Cleveland 1
Dalian 1
Danville 1
Elk Grove Village 1
Esslingen am Neckar 1
Fagnano Castello 1
Totale 2.272
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Nome #
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 145
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 120
An Ultralow-Voltage Energy-Efficient Level Shifter 94
A Framework for Energy-Efficiency in Smart Home Environments 91
A Methodology to Account for the Finger Interruptions in Solar Cell Performance 85
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 84
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 82
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 82
Designing Dynamic Carry Skip Adders: Analysis and Comparison 77
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 76
A comparative study of MWT architectures by means of numerical simulations 72
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 71
Comparative analysis of yield optimized pulsed flip-flops 71
Collaborative Smart Environments for energy-efficiency and quality of life 70
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 70
Design of a sub-1-V nanopower CMOS current reference 68
A portable class of 3-transistor current references with low-power sub-0.5 V operation 67
A methodology to account for the finger non-uniformity in photovoltaic solar cell 66
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 66
Low energy/delay overhead level shifter for wide-range voltage conversion 64
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 63
2-D numerical analysis of the impact of the highly-doped profile on selective emitter solar cell performance 62
Design of a 3T current reference for low-voltage, low-power operation 61
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 61
Design and evaluation of high-speed energy-aware carry skip adders 59
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 59
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 57
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 56
Impact of the Emitter Contact Pattern in c-Si BC-BJ Solar Cells by Numerical Simulations 56
Spin-orbit torque based physical unclonable function 55
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 54
Optimization of Rear Point Contact Geometry by Means of 3-D Numerical Simulation 54
Numerical Simulation and Modeling of Resistive and Recombination Losses in MWT Solar Cells 53
Double-precision Dual Mode Logic carry-save multiplier 53
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs 52
Device-to-system level simulation framework for STT-DMTJ based cache memory 52
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 51
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 51
Two- and three-dimensional numerical simulation of advanced silicon solar cells 50
Evaluating the energy efficiency of stt-mrams based on perpendicular mtjs with double reference layers 49
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 48
Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers 47
Effect of shunt resistance on the performance of mc-Silicon solar cells: A combined electro-optical and thermal investigation 47
Hardware implementation of a Test Lab for Smart Home environments 46
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 45
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 42
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 42
Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis 41
Loss analysis of silicon solar cells by means of numerical device simulation 41
Numerical simulation and modeling of rear point contact solar cells 41
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 40
Numerical simulation on the influence of via and rear emitters in MWT solar cells 40
An energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops 39
Understanding the impact of double screen-printing on silicon solar cells by 2-D numerical simulations 36
Open issues for the numerical simulation of silicon solar cells 32
Design of Ultra-Low Voltage/Power Circuits and Systems 32
Performance analysis of rear point contact solar cells by three-dimensional numerical simulation 29
Understanding the impact of the doping profiles on selective emitter solar cell by two-dimensional numerical simulation 29
Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM 28
Assessment of paper-based MoS2 FET for Physically Unclonable Functions 26
Field-Free Magnetic Tunnel Junction for Logic Operations Based on Voltage-Controlled Magnetic Anisotropy 24
Voltage-controlled magnetic anisotropy based physical unclonable function 22
Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures 22
STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing 21
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V 17
PUF-Based Authentication-Oriented Architecture for Identification Tags 17
Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations 14
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing 13
Experimental analysis of variability in WS2-based devices for hardware security 11
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider 9
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing 7
Totale 3.677
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Categoria #
all - tutte 29.554
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 29.554
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020258 0 0 0 0 22 75 28 33 8 26 46 20
2020/2021367 64 3 45 48 9 38 11 63 8 47 8 23
2021/2022855 20 108 3 45 102 14 10 189 11 27 117 209
2022/2023945 146 91 25 114 150 78 1 120 112 26 35 47
2023/2024591 65 37 37 21 45 74 51 51 52 30 30 98
2024/2025401 28 170 31 90 82 0 0 0 0 0 0 0
Totale 3.677