IRIS
CORSONELLO, Pasquale
 Distribuzione geografica
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Continente #
NA - Nord America 5.614
EU - Europa 3.132
AS - Asia 1.387
AF - Africa 238
SA - Sud America 25
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 8
AN - Antartide 1
Totale 10.416
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Nazione #
US - Stati Uniti d'America 5.462
UA - Ucraina 1.384
DE - Germania 812
SG - Singapore 583
CN - Cina 527
SE - Svezia 337
IT - Italia 273
SN - Senegal 225
TR - Turchia 195
CA - Canada 150
FI - Finlandia 134
BE - Belgio 44
AT - Austria 35
GB - Regno Unito 27
IN - India 22
FR - Francia 19
BR - Brasile 17
HK - Hong Kong 16
RU - Federazione Russa 16
AU - Australia 11
NL - Olanda 9
CZ - Repubblica Ceca 8
EU - Europa 8
EG - Egitto 7
KR - Corea 7
IL - Israele 6
VN - Vietnam 5
ID - Indonesia 4
JP - Giappone 4
PK - Pakistan 4
PL - Polonia 4
TW - Taiwan 4
AL - Albania 3
AR - Argentina 3
ES - Italia 3
LT - Lituania 3
LV - Lettonia 3
MA - Marocco 3
MK - Macedonia 3
BD - Bangladesh 2
CL - Cile 2
GR - Grecia 2
KG - Kirghizistan 2
LU - Lussemburgo 2
PA - Panama 2
PE - Perù 2
RO - Romania 2
TN - Tunisia 2
AZ - Azerbaigian 1
BG - Bulgaria 1
CH - Svizzera 1
CY - Cipro 1
DK - Danimarca 1
EC - Ecuador 1
GS - Georgia del Sud e Isole Sandwich Australi 1
HR - Croazia 1
IE - Irlanda 1
IM - Isola di Man 1
LA - Repubblica Popolare Democratica del Laos 1
MY - Malesia 1
PT - Portogallo 1
RS - Serbia 1
SA - Arabia Saudita 1
SK - Slovacchia (Repubblica Slovacca) 1
TH - Thailandia 1
ZW - Zimbabwe 1
Totale 10.416
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Città #
Chandler 954
Jacksonville 939
Boardman 505
Dearborn 486
Singapore 456
San Mateo 323
Dakar 225
Lawrence 208
Roxbury 208
Izmir 181
Shanghai 166
Ann Arbor 151
Des Moines 139
Helsinki 131
Ottawa 126
Rende 120
Cambridge 113
Bremen 85
Beijing 82
Ogden 75
Ashburn 74
Inglewood 72
Grafing 50
Wilmington 49
New York 48
Brussels 44
Brooklyn 42
Falkenstein 27
Seattle 26
Vienna 26
San Francisco 24
Guangzhou 22
Los Angeles 19
Toronto 17
Norwalk 15
Santa Clara 15
Nanjing 13
Munich 12
Frankfurt am Main 11
Houston 11
Amsterdam 9
Bari 9
Hong Kong 9
Shenzhen 9
Wuhan 9
Hefei 8
Jiaxing 7
Milan 7
Redmond 7
Seoul 7
Woodbridge 7
Duncan 6
Rome 6
Siegen 6
Melbourne 5
Ningbo 5
Olomouc 5
Tappahannock 5
Canberra 4
Central 4
Changsha 4
Chengdu 4
Chicago 4
Dayton 4
Falls Church 4
Hangzhou 4
Hyderabad 4
Jinan 4
London 4
Mascalucia 4
Moscow 4
Naples 4
Scilla 4
Tel Aviv 4
Tradate 4
Berlin 3
Brescia 3
Catanzaro 3
Cerzeto 3
Chennai 3
Chongqing 3
Edinburgh 3
Florence 3
Giza 3
Haikou 3
Hanoi 3
Istanbul 3
Klosterneuburg 3
Lappeenranta 3
Nanchang 3
Palermo 3
Rizziconi 3
Skopje 3
Taizhou 3
Taxila 3
Tirana 3
Visakhapatnam 3
Warsaw 3
Xuzhou 3
Assiut 2
Totale 6.558
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Nome #
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference 104
Design and demonstration of a real time processor for one-bit coded SAR signals 84
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 84
A high-performance fully reconfigurable FPGA-based 2D convolution processor 82
An efficient hardware-oriented single-pass approach for connected component analysis 81
A FPSoC for wavelet-based image compression 81
A 56-bit self-timed adder for high speed asynchronous datapath 80
Radial-Shaped Single Varactor-Tuned Phasing Line for Active Reflectarrays 79
A Matrix Product Accelerator for Field Programmable Systems on Chip 78
High speed division and square root modules for asynchronous datapaths 77
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 77
56-bit self-timed adder for high speed asynchronous datapaths 75
A high-speed energy-efficient 64-bit reconfigurable binary adder 74
Multimodal background subtraction for high-performance embedded systems 73
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 73
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 73
Low-power split-path data-driven dynamic logic 72
Comparative analysis of yield optimized pulsed flip-flops 72
An efficient connected component labeling architecture for embedded systems 72
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 72
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 71
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 71
A New High Performance Circuit for Statistical Carry Lookahead Addition 70
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 69
A novel background subtraction method based on color invariants and grayscale levels 68
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 67
High speed self-timed pipelined datapath for square rooting 67
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 67
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 66
A low-leakage single ended 6T SRAM cell 66
64-bit reconfigurable adder for low power media processing 66
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 66
Techniques for leakage energy reduction in deep submicrometer cache memories 64
High speed self-timed pipelined datapath for square root 64
Design of a reconfigurable reflectarray based on a varactor tuned element 64
A low-cost PSoC architecture for long FFT 64
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 64
CMOS buffer sizing for long on-chip interconnects 63
A new charge-pump based countermeasure against differential power analysis 63
A new type of fast, low-cost binary adder 63
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 63
Low-Power Level Shifter for Multi-Supply Voltage Designs 63
Estimation of Power Dissipation for Trasmission Lines in Deep-Submicrometer ULSI Circuits 62
High performance square rooting circuit using hybrid radix-2 adders 62
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 62
Novel varactor-loaded phasing line for reflectarray unit cell with large reconfigurability frequency range 62
A new noise-tolerant dynamic logic circuit design 62
Active reflectarray element with large reconfigurability frequency range 62
Variable precision arithmetic circuits for FPGA-based multimedia processors 61
Design and demonstration of high throughput square rooting circuit 61
Beam-Scanning Reflectarray based on a single varactor-tuned element 61
Hybrid carry-select statistical carry look-ahead adder 60
A matrix product coprocessor for FPGA embedded soft processors 60
High performance VLSI modules for division and square root 60
Designing Fast Convolutional Engines for Deep Learning Applications 60
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 59
Design of Efficient BCD adders in Quantum Dot Cellular Automata 59
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 59
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 59
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 58
Educational design of high-performance arithmetic circuits on FPGA 58
Design of Real-Time FPGA-based Embedded System for Stereo Vision 58
VLSI circuits for low-power high-speed asynchronous addition 57
Design of efficient QCA multiplexers 57
Efficient VLSI implementation of statistical carry lookahead adder 57
Efficient Recursive Multiply Architecture for FPGAs 56
Estimation of power dissipation for transmission lines in deep-submicrometer ULSI circuits 55
An Efficient Hardware-Oriented Stereo Matching Algorithm 55
Accurate power estimation model for CMOS adders optimization 55
LEWIS project: An integrated system of monitoring, early warning and mitigation of landslides risk 55
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 55
Low bit rate image compression core for onboard space applications 55
An embedded machine vision system for an in-line quality check of assembly processes 55
Area-time-power tradeoff in VLSI cellular arrays implementations 54
Tapered-Vth Approach for Energy-Efficient CMOS Buffers 54
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 54
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 54
A new low-power high-speed single-clock-cycle binary comparator 54
A new reconfigurable coarse-grain architecture for multimedia applications 54
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 54
High speed division and square root modules for asynchronous datapath 53
Area-delay efficient binary adders in QCA 53
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing 53
High throughput combined division square root unit 52
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 52
Designing High-Speed Adders in Power-Constrained Environments 52
Impact of random process variations on different 65nm SRAM cell topologies 51
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates 51
Color Invariant Study for Background Subtraction 50
LEWIS project: An integrated system of monitoring, early warning and mitigation of landslides risk 50
Educational Design of high performance arithmetic circuits 49
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 49
Approximate Multipliers with Dynamic Truncation for Energy Reduction via Graceful Quality Degradation 49
Multimodal background subtraction for high-performance embedded systems 49
New high performance circuit for statistical carry lookahead addition 48
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 48
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 48
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 48
Performance comparison between static and dynamic CMOS logic implementations of a pipelined square-rooting circuit 48
A parallel connected component labeling architecture for heterogeneous systems-on-chip 48
Totale 6.208
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Categoria #
all - tutte 81.890
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 81.890
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.227 0 0 0 0 0 508 126 218 32 40 197 106
2020/20211.520 239 3 192 207 9 195 16 233 23 212 11 180
2021/20221.938 15 241 1 129 193 62 13 382 18 16 305 563
2022/20232.130 250 158 26 256 295 246 7 376 264 79 94 79
2023/20241.147 144 54 103 43 51 84 27 95 127 35 101 283
2024/20251.370 115 570 86 139 293 167 0 0 0 0 0 0
Totale 10.600