IRIS
CORSONELLO, Pasquale
 Distribuzione geografica
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Continente #
NA - Nord America 7.929
AS - Asia 7.538
EU - Europa 4.143
SA - Sud America 2.303
AF - Africa 544
OC - Oceania 17
Continente sconosciuto - Info sul continente non disponibili 13
AN - Antartide 1
Totale 22.488
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Nazione #
US - Stati Uniti d'America 7.570
SG - Singapore 2.984
BR - Brasile 1.669
UA - Ucraina 1.417
CN - Cina 1.353
VN - Vietnam 1.297
DE - Germania 934
HK - Hong Kong 452
IT - Italia 445
SE - Svezia 346
FR - Francia 314
TR - Turchia 248
SN - Senegal 232
AR - Argentina 215
KR - Corea 206
IN - India 196
CA - Canada 183
FI - Finlandia 177
BD - Bangladesh 150
IQ - Iraq 124
GB - Regno Unito 97
ID - Indonesia 97
EC - Ecuador 95
MX - Messico 94
CO - Colombia 89
RU - Federazione Russa 84
ZA - Sudafrica 80
PK - Pakistan 74
VE - Venezuela 72
AT - Austria 54
CL - Cile 53
MA - Marocco 53
BE - Belgio 49
PY - Paraguay 43
UZ - Uzbekistan 42
PL - Polonia 41
NL - Olanda 39
SA - Arabia Saudita 39
EG - Egitto 37
TN - Tunisia 37
ES - Italia 31
PE - Perù 28
PH - Filippine 28
DZ - Algeria 26
MY - Malesia 24
UY - Uruguay 24
KZ - Kazakistan 23
NP - Nepal 23
JO - Giordania 22
JP - Giappone 22
DO - Repubblica Dominicana 20
ET - Etiopia 17
IL - Israele 17
KE - Kenya 17
AE - Emirati Arabi Uniti 15
AU - Australia 15
CR - Costa Rica 14
KG - Kirghizistan 13
OM - Oman 13
BO - Bolivia 11
PA - Panama 11
AZ - Azerbaigian 10
LB - Libano 10
RS - Serbia 10
AL - Albania 9
CH - Svizzera 9
CZ - Repubblica Ceca 9
NI - Nicaragua 9
RO - Romania 9
BG - Bulgaria 8
EU - Europa 8
JM - Giamaica 8
BY - Bielorussia 7
KW - Kuwait 7
MK - Macedonia 7
AM - Armenia 6
CI - Costa d'Avorio 6
GE - Georgia 6
GR - Grecia 5
HN - Honduras 5
IE - Irlanda 5
LT - Lituania 5
LV - Lettonia 5
LY - Libia 5
TW - Taiwan 5
AO - Angola 4
BA - Bosnia-Erzegovina 4
GA - Gabon 4
HR - Croazia 4
IR - Iran 4
KH - Cambogia 4
LK - Sri Lanka 4
PS - Palestinian Territory 4
XK - ???statistics.table.value.countryCode.XK??? 4
BB - Barbados 3
BW - Botswana 3
CG - Congo 3
DK - Danimarca 3
GT - Guatemala 3
MD - Moldavia 3
Totale 22.422
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Città #
Singapore 1.268
Chandler 954
Jacksonville 940
San Jose 601
Boardman 505
Dallas 491
Dearborn 486
Ho Chi Minh City 464
Hong Kong 442
Beijing 365
Ashburn 352
San Mateo 323
Hanoi 287
Dakar 232
Lawrence 208
Roxbury 208
Lauterbourg 205
Seoul 203
Izmir 183
Hefei 182
Shanghai 170
Ann Arbor 151
Helsinki 141
Des Moines 140
Ottawa 128
Rende 127
São Paulo 118
Cambridge 113
New York 88
Bremen 85
Ogden 75
Inglewood 72
Council Bluffs 65
Munich 65
The Dalles 64
Haiphong 61
Da Nang 58
Los Angeles 55
Brooklyn 54
Rio de Janeiro 51
Grafing 50
Columbus 49
Wilmington 49
Brussels 45
Tianjin 44
Milan 42
Guangzhou 40
Santa Clara 38
Baghdad 37
Tashkent 37
Frankfurt am Main 35
San Francisco 34
Vienna 34
Quito 33
Seattle 33
Dhaka 32
Biên Hòa 31
Catanzaro 30
Falkenstein 30
Turku 30
Guayaquil 29
Johannesburg 28
Campinas 27
Warsaw 27
Belo Horizonte 26
Mexico City 26
Chennai 25
Orem 25
Curitiba 24
Caracas 23
Hải Dương 23
Toronto 23
Brasília 22
Salvador 22
Thái Bình 22
Amsterdam 21
Lahore 21
Nuremberg 21
Amman 20
Asunción 20
Chicago 20
Guarulhos 20
Medellín 20
Bogotá 19
Lima 19
Montevideo 19
Santiago 19
Can Tho 18
Cape Town 18
Istanbul 18
London 18
Porto Alegre 17
Quảng Ngãi 17
Shenzhen 17
Addis Ababa 16
Karachi 16
New Delhi 16
Tunis 16
Bari 15
Buenos Aires 15
Totale 12.361
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Nome #
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference 190
A high-performance fully reconfigurable FPGA-based 2D convolution processor 184
A Matrix Product Accelerator for Field Programmable Systems on Chip 163
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 162
A 56-bit self-timed adder for high speed asynchronous datapath 161
A FPSoC for wavelet-based image compression 160
A high-speed energy-efficient 64-bit reconfigurable binary adder 158
Design and demonstration of a real time processor for one-bit coded SAR signals 152
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 151
56-bit self-timed adder for high speed asynchronous datapaths 150
A new reconfigurable coarse-grain architecture for multimedia applications 149
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 145
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 145
An efficient hardware-oriented single-pass approach for connected component analysis 143
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 140
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 140
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 139
64-bit reconfigurable adder for low power media processing 139
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 137
A new low-power high-speed single-clock-cycle binary comparator 137
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 136
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 135
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 134
A matrix product coprocessor for FPGA embedded soft processors 134
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 133
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 132
High speed division and square root modules for asynchronous datapaths 131
CMOS buffer sizing for long on-chip interconnects 130
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 130
A low-leakage single ended 6T SRAM cell 130
A new charge-pump based countermeasure against differential power analysis 129
An efficient connected component labeling architecture for embedded systems 129
A New High Performance Circuit for Statistical Carry Lookahead Addition 128
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 128
Multimodal background subtraction for high-performance embedded systems 127
A novel background subtraction method based on color invariants and grayscale levels 127
Radial-Shaped Single Varactor-Tuned Phasing Line for Active Reflectarrays 126
A new noise-tolerant dynamic logic circuit design 125
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 122
An efficient wavelet image encoder for FPGA-based design 121
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 121
Techniques for leakage energy reduction in deep submicrometer cache memories 120
Design and demonstration of high throughput square rooting circuit 120
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 120
An explainable embedded neural system for on-board ship detection from optical satellite imagery 119
High throughput combined division square root unit 119
A parallel connected component labeling architecture for heterogeneous systems-on-chip 119
High speed self-timed pipelined datapath for square rooting 118
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 118
Novel varactor-loaded phasing line for reflectarray unit cell with large reconfigurability frequency range 117
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 116
Comparative analysis of yield optimized pulsed flip-flops 115
Design of a reconfigurable reflectarray based on a varactor tuned element 115
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 115
Design of Real-Time FPGA-based Embedded System for Stereo Vision 115
Variable precision arithmetic circuits for FPGA-based multimedia processors 114
Low-Power Level Shifter for Multi-Supply Voltage Designs 113
A low-cost PSoC architecture for long FFT 113
An efficient convolution engine based on the à-trous spatial pyramid pooling 113
Accurate power estimation model for CMOS adders optimization 112
Compressed Sensing Approach for Physiological Signals: A Review 110
Low-power split-path data-driven dynamic logic 110
High performance VLSI modules for division and square root 110
Active reflectarray element with large reconfigurability frequency range 109
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 109
A new type of fast, low-cost binary adder 108
Hybrid carry-select statistical carry look-ahead adder 107
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 107
Beam-Scanning Reflectarray based on a single varactor-tuned element 107
An efficient self-timed adder realized using conventional CMOS standard cells 106
New methodology for the design of efficient binary addition circuits in QCA 106
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 105
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals 105
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 104
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 104
Educational Design of high performance arithmetic circuits 104
An Efficient Hardware-Oriented Stereo Matching Algorithm 104
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 104
Low bit rate image compression core for onboard space applications 104
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 104
New high performance circuit for statistical carry lookahead addition 103
Fast, low-cost adders using carry-strength signals 103
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 102
LEWIS project: An integrated system of monitoring, early warning and mitigation of landslides risk 102
Educational design of high-performance arithmetic circuits on FPGA 102
Efficient VLSI implementation of statistical carry lookahead adder 102
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 102
ECG Signals Analysis based on Compressed Sensing and Learning Techniques for Heart Disease Recognition 101
VLSI circuits for low-power high-speed asynchronous addition 101
Design of efficient QCA multiplexers 101
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 101
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations 100
Area-time-power tradeoff in VLSI cellular arrays implementations 100
Dynamic Power of CMOS Gates Driving Lossy Transmission Lines 100
LEWIS project: An integrated system of monitoring, early warning and mitigation of landslides risk 100
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 100
High speed division and square root modules for asynchronous datapath 99
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 99
Estimation of power dissipation for transmission lines in deep-submicrometer ULSI circuits 98
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems 98
Totale 12.105
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Categoria #
all - tutte 130.948
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 130.948
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021403 0 0 0 0 0 0 0 0 0 212 11 180
2021/20221.938 15 241 1 129 193 62 13 382 18 16 305 563
2022/20232.130 250 158 26 256 295 246 7 376 264 79 94 79
2023/20241.147 144 54 103 43 51 84 27 95 127 35 101 283
2024/20253.488 115 570 86 139 293 173 113 265 483 135 327 789
2025/20269.983 1.296 515 926 1.307 1.965 672 1.134 534 769 865 0 0
Totale 22.701