IRIS
CORSONELLO, Pasquale
 Distribuzione geografica
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Continente #
NA - Nord America 8.598
AS - Asia 7.784
EU - Europa 4.245
SA - Sud America 2.304
AF - Africa 547
OC - Oceania 19
Continente sconosciuto - Info sul continente non disponibili 13
AN - Antartide 1
Totale 23.511
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Nazione #
US - Stati Uniti d'America 8.197
SG - Singapore 3.020
BR - Brasile 1.669
CN - Cina 1.431
UA - Ucraina 1.417
VN - Vietnam 1.300
DE - Germania 934
IT - Italia 540
HK - Hong Kong 458
SE - Svezia 346
FR - Francia 314
BD - Bangladesh 252
TR - Turchia 248
SN - Senegal 232
AR - Argentina 215
KR - Corea 207
CA - Canada 198
IN - India 196
FI - Finlandia 177
IQ - Iraq 124
GB - Regno Unito 99
ID - Indonesia 99
EC - Ecuador 95
MX - Messico 95
CO - Colombia 89
RU - Federazione Russa 84
ZA - Sudafrica 80
PK - Pakistan 75
VE - Venezuela 73
AT - Austria 54
CL - Cile 53
MA - Marocco 53
BE - Belgio 51
PY - Paraguay 43
UZ - Uzbekistan 42
PL - Polonia 41
NL - Olanda 40
SA - Arabia Saudita 39
TN - Tunisia 38
EG - Egitto 37
ES - Italia 32
MY - Malesia 29
PE - Perù 28
PH - Filippine 28
DZ - Algeria 27
NP - Nepal 27
JP - Giappone 25
UY - Uruguay 24
KZ - Kazakistan 23
JO - Giordania 22
DO - Repubblica Dominicana 20
AE - Emirati Arabi Uniti 19
CR - Costa Rica 17
ET - Etiopia 17
IL - Israele 17
KE - Kenya 17
AU - Australia 16
KG - Kirghizistan 13
OM - Oman 13
JM - Giamaica 12
BO - Bolivia 11
NI - Nicaragua 11
PA - Panama 11
AZ - Azerbaigian 10
LB - Libano 10
RS - Serbia 10
AL - Albania 9
CH - Svizzera 9
CZ - Repubblica Ceca 9
HN - Honduras 9
RO - Romania 9
BG - Bulgaria 8
EU - Europa 8
BY - Bielorussia 7
KW - Kuwait 7
MK - Macedonia 7
AM - Armenia 6
CI - Costa d'Avorio 6
GE - Georgia 6
GT - Guatemala 6
SV - El Salvador 6
BB - Barbados 5
GR - Grecia 5
IE - Irlanda 5
LT - Lituania 5
LV - Lettonia 5
LY - Libia 5
TW - Taiwan 5
AO - Angola 4
BA - Bosnia-Erzegovina 4
GA - Gabon 4
HR - Croazia 4
IR - Iran 4
KH - Cambogia 4
LK - Sri Lanka 4
MD - Moldavia 4
PS - Palestinian Territory 4
XK - ???statistics.table.value.countryCode.XK??? 4
BW - Botswana 3
CG - Congo 3
Totale 23.437
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Città #
Singapore 1.273
Chandler 954
Jacksonville 942
San Jose 630
Boardman 505
Dallas 492
Dearborn 486
Ho Chi Minh City 465
Hong Kong 447
Ashburn 401
Beijing 376
Council Bluffs 347
San Mateo 323
Hanoi 289
Dakar 232
Lawrence 208
Roxbury 208
Lauterbourg 205
Seoul 203
Izmir 183
Hefei 182
Shanghai 171
Ann Arbor 151
Helsinki 141
Des Moines 140
New York 137
Ottawa 129
Rende 128
São Paulo 118
Cambridge 113
Bremen 85
Columbus 80
Ogden 75
Inglewood 72
Santa Clara 66
Munich 65
The Dalles 64
Los Angeles 62
Haiphong 61
Da Nang 58
Brooklyn 55
Rio de Janeiro 51
Grafing 50
Wilmington 49
Milan 47
Tianjin 46
Brussels 45
Guangzhou 41
Baghdad 37
San Francisco 37
Tashkent 37
Frankfurt am Main 35
Seattle 34
Vienna 34
Dhaka 33
Quito 33
Biên Hòa 31
Catanzaro 30
Falkenstein 30
Turku 30
Guayaquil 29
Johannesburg 28
Campinas 27
Mexico City 27
Warsaw 27
Belo Horizonte 26
Chicago 26
Rome 26
Toronto 26
Chennai 25
Orem 25
Curitiba 24
Caracas 23
Hải Dương 23
Brasília 22
Buffalo 22
Salvador 22
Thái Bình 22
Amsterdam 21
Lahore 21
Nuremberg 21
Amman 20
Asunción 20
Guarulhos 20
Medellín 20
Bogotá 19
Lima 19
Montevideo 19
Naples 19
Santiago 19
Can Tho 18
Cape Town 18
Istanbul 18
London 18
Shenzhen 18
Bari 17
Porto Alegre 17
Quảng Ngãi 17
Tunis 17
Addis Ababa 16
Totale 12.914
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Nome #
A high-performance fully reconfigurable FPGA-based 2D convolution processor 200
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference 194
A Matrix Product Accelerator for Field Programmable Systems on Chip 183
A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers 168
A FPSoC for wavelet-based image compression 165
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations 163
A 56-bit self-timed adder for high speed asynchronous datapath 162
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems 161
A high-speed energy-efficient 64-bit reconfigurable binary adder 160
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs 158
A new reconfigurable coarse-grain architecture for multimedia applications 155
56-bit self-timed adder for high speed asynchronous datapaths 154
Design and demonstration of a real time processor for one-bit coded SAR signals 153
Multimodal background subtraction for high-performance embedded systems 148
An efficient hardware-oriented single-pass approach for connected component analysis 148
A high flexible early-late gate bit synchronizer in FPGA-based software defined radios 148
64-bit reconfigurable adder for low power media processing 143
A new dynamic logic circuit design for an effective trade-off between noise-immunity, performance and energy dissipation 143
A new scheme to reduce leakage in deep-submicron cache memories with no extra dynamic consumption 140
A high flexible 8-bit and 16-bit SIMD soft microcontroller for FPGAs 139
A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation 139
A Low-Power Sub-Nanosecond Standard-Cells Based Adder 138
A new low-power high-speed single-clock-cycle binary comparator 138
A Microchip Integrated Sensor for the Monitoring of High Concentration Photo-voltaic Solar Modules 138
An efficient connected component labeling architecture for embedded systems 138
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 137
A layout strategy for low-power voltage level shifters in 28nm UTBB FDSOI technology 137
A microchip integrated wireless sensor for the monitoring of high concentration photo-voltaic solar cells 136
A matrix product coprocessor for FPGA embedded soft processors 136
Analyzing noise-robustness of wide fan-in dynamic logic gates under process variations 135
Fast and Wide Range Voltage Conversion in Multi-Supply Voltage Designs 134
A new noise-tolerant dynamic logic circuit design 132
A low-leakage single ended 6T SRAM cell 132
High speed division and square root modules for asynchronous datapaths 131
CMOS buffer sizing for long on-chip interconnects 131
Radial-Shaped Single Varactor-Tuned Phasing Line for Active Reflectarrays 130
Analytical Delay Model Considering Variability Effects in Subthreshold Domain 129
A novel background subtraction method based on color invariants and grayscale levels 129
An efficient wavelet image encoder for FPGA-based design 129
A new charge-pump based countermeasure against differential power analysis 129
A New High Performance Circuit for Statistical Carry Lookahead Addition 129
Low-power split-path data-driven dynamic logic 128
Compressed Sensing Approach for Physiological Signals: A Review 126
Techniques for leakage energy reduction in deep submicrometer cache memories 126
A parallel connected component labeling architecture for heterogeneous systems-on-chip 125
An explainable embedded neural system for on-board ship detection from optical satellite imagery 124
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations 123
High speed self-timed pipelined datapath for square rooting 122
Accuracy Improved Low-Energy Multi-bit Approximate Adders in QCA 122
Design and demonstration of high throughput square rooting circuit 121
High throughput combined division square root unit 120
Comparative analysis of yield optimized pulsed flip-flops 120
Design of Real-Time FPGA-based Embedded System for Stereo Vision 120
An efficient convolution engine based on the à-trous spatial pyramid pooling 120
Variable precision arithmetic circuits for FPGA-based multimedia processors 119
Novel varactor-loaded phasing line for reflectarray unit cell with large reconfigurability frequency range 119
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems 119
Low-Power Level Shifter for Multi-Supply Voltage Designs 118
Design of a real-time face detection architecture for heterogeneous systems-on-chips 118
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations 117
Design of a reconfigurable reflectarray based on a varactor tuned element 117
An Efficient and Low-Cost Design Methodology to Improve SRAM-based FPGA Robustness in Space and Avionics Applications 117
A low-cost PSoC architecture for long FFT 116
Accurate power estimation model for CMOS adders optimization 115
Low bit rate image compression core for onboard space applications 115
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals 115
High performance VLSI modules for division and square root 114
Hybrid carry-select statistical carry look-ahead adder 113
VLSI Implementation of a Fully Static CMOS 56-bit Self-Timed Adder Using Overlapped Execution Circuits 113
Active reflectarray element with large reconfigurability frequency range 112
Custom Computing Reconfigurable Machine for High Performance Cellular Automata Processing 111
New methodology for the design of efficient binary addition circuits in QCA 111
A Self-Hosting Configuration Management System to Mitigate the Impact of Radiation-Induced Multi-Bit Upsets in SRAM-Based FPGAs 110
Low Leakage SRAM Wordline Drivers for the 28nm UTBB FDSOI Technology 110
Adaptive Census transform: A novel hardware-oriented stereovision algorithm 109
A new type of fast, low-cost binary adder 109
Educational design of high-performance arithmetic circuits on FPGA 109
An efficient self-timed adder realized using conventional CMOS standard cells 109
Beam-Scanning Reflectarray based on a single varactor-tuned element 109
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation 109
Design and Implementation of a Low Bit-Rate On-Board Satellite Wavelet-based Compression Core 108
Design of High-Speed Low-Power Parallel-prefix Adder Trees in Nanometer Technologies 107
Educational Design of high performance arithmetic circuits 107
High-performance noise-tolerant circuit techniques for CMOS dynamic logic 107
Multimodal background subtraction for high-performance embedded systems 107
Efficient deconvolution architecture for heterogeneous systems-on-chip 107
ECG Signals Analysis based on Compressed Sensing and Learning Techniques for Heart Disease Recognition 106
Design of efficient QCA multiplexers 106
LEWIS project: An integrated system of monitoring, early warning and mitigation of landslides risk 105
Efficient VLSI implementation of statistical carry lookahead adder 105
Fully-Synthesizable Reconfigurable Multiplier for High-Performance Multimedia Processors 105
Abnormal ECG Detection in Wearable Devices Using Compressed Learning 104
New high performance circuit for statistical carry lookahead addition 104
An Efficient Hardware-Oriented Stereo Matching Algorithm 104
Fast, low-cost adders using carry-strength signals 104
High speed self-timed pipelined datapath for square root 103
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics 103
LEWIS project: An integrated system of monitoring, early warning and mitigation of landslides risk 103
Energy‐efficient architecture for CNNs inference on heterogeneous FPGA 103
Design of a Low-Power Super-Resolution Architecture for Virtual Reality Wearable Devices 102
Totale 12.642
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Categoria #
all - tutte 137.122
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 137.122
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021180 0 0 0 0 0 0 0 0 0 0 0 180
2021/20221.938 15 241 1 129 193 62 13 382 18 16 305 563
2022/20232.130 250 158 26 256 295 246 7 376 264 79 94 79
2023/20241.147 144 54 103 43 51 84 27 95 127 35 101 283
2024/20253.488 115 570 86 139 293 173 113 265 483 135 327 789
2025/202611.008 1.296 515 926 1.307 1.965 672 1.134 534 769 902 493 495
Totale 23.726