IRIS
CRUPI, Felice
 Distribuzione geografica
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Continente #
NA - Nord America 11.006
AS - Asia 6.360
EU - Europa 4.329
SA - Sud America 1.837
AF - Africa 366
Continente sconosciuto - Info sul continente non disponibili 20
OC - Oceania 16
AN - Antartide 1
Totale 23.935
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Nazione #
US - Stati Uniti d'America 10.714
SG - Singapore 3.037
UA - Ucraina 1.487
BR - Brasile 1.416
CN - Cina 1.180
DE - Germania 1.148
VN - Vietnam 836
IT - Italia 483
SE - Svezia 393
HK - Hong Kong 317
FI - Finlandia 277
KR - Corea 246
TR - Turchia 230
CA - Canada 194
AR - Argentina 184
SN - Senegal 173
BD - Bangladesh 90
GB - Regno Unito 89
RU - Federazione Russa 86
IQ - Iraq 83
IN - India 81
EC - Ecuador 65
ZA - Sudafrica 60
MX - Messico 59
BE - Belgio 58
AT - Austria 55
NL - Olanda 47
FR - Francia 43
ID - Indonesia 43
CO - Colombia 39
CZ - Repubblica Ceca 37
VE - Venezuela 35
PL - Polonia 30
PY - Paraguay 29
MA - Marocco 27
JP - Giappone 25
PK - Pakistan 25
PE - Perù 23
CL - Cile 22
DZ - Algeria 20
AE - Emirati Arabi Uniti 19
KE - Kenya 19
UZ - Uzbekistan 18
EG - Egitto 17
TN - Tunisia 17
UY - Uruguay 17
EU - Europa 16
JO - Giordania 16
AU - Australia 15
AZ - Azerbaigian 14
ES - Italia 13
IE - Irlanda 13
NP - Nepal 10
TW - Taiwan 10
IL - Israele 9
LT - Lituania 9
DO - Repubblica Dominicana 8
ET - Etiopia 8
KZ - Kazakistan 8
OM - Oman 8
SA - Arabia Saudita 8
BG - Bulgaria 7
BO - Bolivia 7
AL - Albania 6
BY - Bielorussia 6
JM - Giamaica 6
MY - Malesia 6
PA - Panama 6
AO - Angola 5
GE - Georgia 5
GR - Grecia 5
HN - Honduras 5
RO - Romania 5
BW - Botswana 4
CR - Costa Rica 4
GA - Gabon 4
LB - Libano 4
QA - Qatar 4
BH - Bahrain 3
CH - Svizzera 3
HU - Ungheria 3
KG - Kirghizistan 3
KH - Cambogia 3
LK - Sri Lanka 3
NG - Nigeria 3
RS - Serbia 3
SK - Slovacchia (Repubblica Slovacca) 3
TT - Trinidad e Tobago 3
AM - Armenia 2
BA - Bosnia-Erzegovina 2
BB - Barbados 2
CI - Costa d'Avorio 2
CY - Cipro 2
DK - Danimarca 2
KW - Kuwait 2
LA - Repubblica Popolare Democratica del Laos 2
LV - Lettonia 2
MD - Moldavia 2
MK - Macedonia 2
MN - Mongolia 2
Totale 23.901
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Città #
Dallas 3.900
Singapore 1.126
Jacksonville 1.077
Chandler 953
Dearborn 552
Boardman 543
San Mateo 417
Beijing 327
Ho Chi Minh City 313
Hong Kong 292
Helsinki 254
Ashburn 248
Roxbury 239
Lawrence 236
Seoul 212
Izmir 208
Shanghai 198
Hanoi 192
Dakar 173
Des Moines 149
Hefei 148
Ottawa 143
São Paulo 125
Munich 124
Ann Arbor 122
New York 104
Rende 99
Inglewood 91
Cambridge 90
Wilmington 89
Brooklyn 86
Council Bluffs 72
Falkenstein 71
Bremen 70
Ogden 68
Grafing 58
Brussels 53
Los Angeles 52
Rio de Janeiro 45
Vienna 41
Milan 40
Chicago 39
Da Nang 39
The Dalles 37
Columbus 36
Haiphong 36
San Francisco 36
Baghdad 33
Cosenza 33
Amsterdam 31
Santa Clara 31
Brno 30
Brasília 29
Pohang 28
Belo Horizonte 27
Curitiba 27
Warsaw 27
Bari 26
Biên Hòa 26
Tianjin 26
Guayaquil 25
Johannesburg 22
Cape Town 21
Dhaka 19
Frankfurt am Main 19
Guangzhou 19
Hải Dương 19
Turku 19
Ninh Bình 18
Rome 18
West Jordan 18
Catanzaro 17
Falls Church 17
Guarulhos 17
Lima 17
London 17
Quito 17
Salvador 17
Tashkent 17
Mexico City 16
Montreal 16
Redwood City 16
Amman 15
Boston 15
Montevideo 15
Nairobi 15
Norwalk 15
Toronto 15
Baku 14
Thái Bình 14
Tokyo 14
Asunción 13
Ribeirão Preto 13
Seattle 13
Jinan 12
Sorocaba 12
Stockholm 12
Bologna 11
Campinas 11
Caxias do Sul 11
Totale 14.638
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Nome #
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm2 Area in 180nm 1.454
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS 1.405
A 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization 1.398
1/f Noise in Drain and Gate Current of MOSFETs With High-k Gate Stacks 173
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference 168
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC 155
An Ultralow-Voltage Energy-Efficient Level Shifter 152
A Methodology to Account for the Finger Interruptions in Solar Cell Performance 141
A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs 139
A model for current conduction after soft-breakdown 138
A detailed analysis of the pre-breakdown current fluctuations in thin oxide MOS capacitors 137
A comparative study of MWT architectures by means of numerical simulations 137
Accountability of IoT Devices 136
A Physical Unclonable Function Based on a 2-Transistor Subthreshold Voltage Divider 135
Analytical model for the 1/f noise in the tunneling current through metal-oxide-semiconductor structures 131
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits 131
Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework 130
A Microscopically Accurate Model of Partially Ballistic NanoMOSFETs in Saturation Based on Channel Backscattering 128
A Defect-Centric Analysis of the Temperature Dependence of the Channel Hot Carrier Degradation in nMOSFETs 128
A Backscattering Model Incorporating the Effective Carrier Temperature in Nano-MOSFET 125
Reconfigurable Intelligent Surface-Aided Indoor Radar Monitoring: A Feasibility Study 123
A Defect-Centric perspective on channel hot carrier variability in nMOSFETs 123
A model for MOS gate stack quality evaluation based on the gate current 1/f noise 122
Improved trade-off between noise and bandwidth in op-amp based transimpedance amplifier 121
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy 121
A new circuit topology for the realization of very low-noise wide-bandwidth transimpedance amplifier 120
A new method for high-sensitivity noise measurements 119
A methodology to account for the finger non-uniformity in photovoltaic solar cell 119
An algorithm for separating multilevel random telegraph signal from 1/f noise 118
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework 117
A comparative study of the oxide breakdown in short-channel nMOSFETs and pMOSFETs stressed in inversion and in accumulation regimes 115
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm 113
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmentic circuits 112
A variation-aware simulation framework for hybrid CMOS/spintronic circuits 110
A portable class of 3-transistor current references with low-power sub-0.5 V operation 110
Influence of GaN- and Si 3 N 4 -Passivation layers on the performance of AlGaN/GaN diodes with a gated edge termination 110
Opto-electrical modelling and optimization study of a novel IBC c-Si solar cell 109
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter 107
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs 106
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions 106
Reliability in GaN-based devices for power applications 106
Spin-orbit torque based physical unclonable function 106
New insights into the relation between channel hot carrier degradation and oxide breakdown in short channel nMOSFETs 105
Characterization of interface and oxide traps in Ge pMOSFETs based on DCIV technique 104
Design of a sub-1-V nanopower CMOS current reference 104
Transients during pre-breakdown and hard breakdown of thin gate oxides in metal-SiO2-Si capacitors 103
A virtual III-V tunnel FET technology platform for ultra-low voltage comparators and level shifters 103
Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework 103
Reliability improvements in AlGaN/GaN schottky barrier diodes with a gated edge termination 103
Automatic radar-based 2-D localization exploiting vital signs signatures 102
A Procedure For Extracting 1/f Noise From Random Telegraph Signals 101
Low energy/delay overhead level shifter for wide-range voltage conversion 100
A tool to support harbor terminals design 99
Assessment of 2D-FET Based Digital and Analog Circuits on Paper 99
PUF-Based Authentication-Oriented Architecture for Identification Tags 98
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW 97
A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks 97
Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium-based gate dielectrics 96
Modeling the gate current 1/f noise and its application to advanced CMOS devices 96
Device-to-system level simulation framework for STT-DMTJ based cache memory 96
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits 95
Impact of the variable output resistance on the transient response of LC transmission line CMOS buffers and its model 95
Strumento elettronico ad elevatissima sensibilità per misura del rumore di tensione di un bipolo 95
Understanding the impact of point-contact scheme and selective emitter in a c-Si BC-BJ solar cell by full 3D numerical simulations 95
Enhanced sensitivity cross-correlation method for voltage noise measurements 95
Chip/Package/Board Co-Simulation Methodology for Crosstalk between DC/DC Converter and ADC Input Channels 95
Full Model and Characterization of Noise in Operational Amplifier 94
Dedicated probe system for wafer level noise measurements in MOS devices 94
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines 94
Design guidelines for a metallization scheme with multiple-emitter contact lines in BC-BJ solar cells 94
Electrical and thermal transient during dielectric breakdown of thin oxides in metal-SiO2-silicon capacitors 94
A new method for high sensitivity noise measurements 94
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits 94
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs 92
Design of a 3T current reference for low-voltage, low-power operation 92
Ultrasensitive low noise voltage amplifier for spectral analysis 92
Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics 91
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits 91
Radiation Tolerance of NROM Embedded Products 90
Performance of current mirror with high-k gate dielectrics 89
A novel methodology for sensing the breakdown location and its application to the reliability study of ultrathin Hf-silicate gate dielectrics 89
Impact of Scaling on Physical Unclonable Function Based on Spin-Orbit Torque 89
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 88
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework 88
A picopower temperature-compensated, subthreshold CMOS voltage reference 86
Three-channel amplifier for high-sensitivity voltage noise measurements 86
Early Assessment of Tunnel-FET for Energy-Efficient Logic Circuits 85
How to Enlarge the Bandwidth without Increasing the Noise in Op-Amp based Transimpedance Amplifier 85
Noise as a probe of the charge transport mechanisms through thin oxides in mos structures 85
Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations 84
A new physically-based model for temperature acceleration of time-to-breakdown 83
Dedicated instrumentation for single-electron effects detection in Si nanocrystal memories 83
Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications 83
Ultrasensitive method for current noise measurements 82
Positive Bias Temperature Instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics 82
Design of a 75 nW, 0.5 V Subthreshold CMOS Operational Amplifier 82
A new technique for extracting the MOSFET threshold voltage using noise measurements 81
Multiple gate NVM cells with improved Fowler-Nordheim tunneling program and erase performances 81
Numerical Simulation and Modeling of Resistive and Recombination Losses in MWT Solar Cells 81
Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology 81
Totale 14.509
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Categoria #
all - tutte 142.757
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 142.757
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021970 0 0 0 0 0 232 16 249 24 231 17 201
2021/20222.150 36 153 7 160 236 78 22 490 33 46 330 559
2022/20232.271 420 171 35 280 330 200 1 311 268 67 90 98
2023/20241.602 166 130 97 63 119 149 105 147 143 82 73 328
2024/20253.504 125 571 66 200 176 316 177 225 528 122 295 703
2025/202610.180 1.424 1.159 3.692 1.333 2.058 514 0 0 0 0 0 0
Totale 24.183